[PATCH] D18492: [X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 27 08:41:06 PDT 2016
RKSimon updated this revision to Diff 51737.
RKSimon added a comment.
Updated based on Chandler's feedback.
Regarding adding support for shifts - I have looked at this (and for add/sub too), but the problem I was seeing was that typicallly one of the elements (#0 most often) didn't share the opcode (i.e. zero shift / offset). I'd be willing to do this for a single 'mis-match' but am worried that it will set a precedent for further relaxations to try and force a vectorization.
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