[PATCH] D18421: [WIP] MachineFunction Properties
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 25 17:41:50 PDT 2016
> On Mar 25, 2016, at 5:36 PM, Derek Schuff <dschuff at google.com> wrote:
> dschuff added a comment.
> Thanks for the reviews!
> There's one more thing this change needs before it can land, and that's a representation in MIR for the properties. Conveniently, my reviewer is an expert on the subject :)
> Here's one possible MIR representation, which just adds `allVRegsAllocated` as another optional top-level tag for the function for each property (and which would also retain compatibility with MIR for e.g. isSSA). Do you think it should also have its own namespace like frameInfo, or maybe its own initialization routine like MIRParserImpl::initializeRegisterInfo?
For now, the representation you chose is fine.
We will revisit when we get more properties.
> Comment at: include/llvm/CodeGen/MachineFunction.h:98
> @@ +97,3 @@
> + BitVector Properties =
> + BitVector(static_cast<unsigned>(Property::LastProperty));
> + // Stated in "positive" form; i.e. a pass could require that the property
> qcolombet wrote:
>> Just a remark: if we want to give more control to the targets with possible properties, we can make the universe of the BitVector an argument of the constructor and just assert that the universe supports at least LastProperty elements.
> Sounds good, I added possible future TODOs in a comment.
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