[llvm] r264282 - [PowerPC] Disable direct moves for extractelement and bitcast in 32-bit mode

[Nemanja Ivanovic via llvm-commits]

Author: nemanjai
Date: Thu Mar 24 08:40:33 2016
New Revision: 264282

URL: http://llvm.org/viewvc/llvm-project?rev=264282&view=rev
Log:
[PowerPC] Disable direct moves for extractelement and bitcast in 32-bit mode

This patch corresponds to review:
http://reviews.llvm.org/D17711

It disables direct moves on these operations in 32-bit mode since the patterns
assume 64-bit registers. The final patch is slightly different from the
Phabricator review as the bitcast operations needed to be disabled in 32-bit
mode as well. This fixes PR26617.

Added:
    llvm/trunk/test/CodeGen/PowerPC/pr26617.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=264282&r1=264281&r2=264282&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Mar 24 08:40:33 2016
@@ -255,7 +255,7 @@ PPCTargetLowering::PPCTargetLowering(con
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
 
-  if (Subtarget.hasDirectMove()) {
+  if (Subtarget.hasDirectMove() && isPPC64) {
     setOperationAction(ISD::BITCAST, MVT::f32, Legal);
     setOperationAction(ISD::BITCAST, MVT::i32, Legal);
     setOperationAction(ISD::BITCAST, MVT::i64, Legal);
@@ -557,7 +557,7 @@ PPCTargetLowering::PPCTargetLowering(con
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
-      if (Subtarget.hasDirectMove()) {
+      if (Subtarget.hasDirectMove() && isPPC64) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);

Added: llvm/trunk/test/CodeGen/PowerPC/pr26617.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr26617.ll?rev=264282&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr26617.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/pr26617.ll Thu Mar 24 08:40:33 2016
@@ -0,0 +1,15 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
+define i32 @test(<4 x i32> %v, i32 %elem) #0 {
+entry:
+  %vecext = extractelement <4 x i32> %v, i32 %elem
+  ret i32 %vecext
+}
+; CHECK: stxvw4x 34,
+; CHECK: lwzx 3,
+
+define float @test2(i32 signext %a) {
+entry:
+  %conv = bitcast i32 %a to float
+  ret float %conv
+}
+; CHECK-NOT: mtvsr