[PATCH] D18426: Remove unsafe AssertZext after promoting result of FP_TO_FP16

[Pirama Arumuga Nainar via llvm-commits]

pirama created this revision.
pirama added reviewers: jmolloy, sbaranga, kristof.beyls, aadg.
pirama added subscribers: srhines, llvm-commits.
Herald added a subscriber: aemerson.

Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32
instruction, do not guarantee that the top 16 bits are zeroed out.
Remove the unsafe AssertZext and add tests to exercise this.

http://reviews.llvm.org/D18426

Files:
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  test/CodeGen/ARM/fp16-v3.ll

Index: test/CodeGen/ARM/fp16-v3.ll
===================================================================
--- test/CodeGen/ARM/fp16-v3.ll
+++ test/CodeGen/ARM/fp16-v3.ll
@@ -25,4 +25,16 @@
   ret void
 }
 
+; CHECK-LABEL: test_bitcast:
+; CHECK: vcvtb.f16.f32
+; CHECK: vcvtb.f16.f32
+; CHECK: vcvtb.f16.f32
+; CHECK: pkhbt
+; CHECK: uxth
+define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
+  %bc = bitcast <3 x half> %inp to <3 x i16>
+  store <3 x i16> %bc, <3 x i16>* %arr, align 8
+  ret void
+}
+
 attributes #0 = { nounwind }
Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -436,10 +436,7 @@
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDLoc dl(N);
 
-  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
-
-  return DAG.getNode(ISD::AssertZext, dl,
-                     NVT, Res, DAG.getValueType(N->getValueType(0)));
+  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {


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