[PATCH] D18237: [SLPVectorizer] Change MinVecRegSize from 128 bits to 64 bits

[Jongwon Lee via llvm-commits]

JongwonLee marked 7 inline comments as done.

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Comment at: lib/Transforms/Vectorize/SLPVectorizer.cpp:3427
@@ +3426,3 @@
+    // <2 x 32-bit data type>, <4 x 16-bit data type>, <8 x 8-bit data type>.
+    llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
+    bool IsAArch64 = TargetTriple.getArch() == llvm::Triple::aarch64 ||
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mcrosier wrote:
> I'm thinking this should be a TTI hook, so each target can define the MinVecRegSize.
I'll separate this from the current patch. The current patch will only handle the range of the size of vectorizable registers.

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Comment at: lib/Transforms/Vectorize/SLPVectorizer.cpp:3747
@@ -3727,3 +3746,3 @@
 
   // FIXME: Register size should be a parameter to this function, so we can
   // try different vectorization factors.
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mcrosier wrote:
> I believe you've addressed this fix me, correct?
Yes. The comment are removed.


http://reviews.llvm.org/D18237