[PATCH] D15256: ARM: Better codegen for 64-bit compares.

Peter Collingbourne via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 18 16:01:48 PDT 2016

pcc marked 2 inline comments as done.

Comment at: lib/Target/ARM/ARMISelLowering.cpp:4719
@@ +4718,3 @@
+  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+  SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
+                                   Cmp.getValue(1), SDValue());
jmolloy wrote:
> This seems fishy to me. Shouldn't we be chaining to DAG.getRoot() (maybe?), rather than getEntryNode()? 
> Surely we want CPSR's value just before the SETCCE, not at the start of the BB?
The correct ordering is created by the edge from the SUBE to the copy. I don't think the chain edge is significant here.

Using the graph root wouldn't be correct, as that would create cycles in the graph.

I'm also not sure if using the entry node is entirely correct, but in my defense, there seems to be similar code in other backends [1].

[1] http://llvm-cs.pcc.me.uk/?q=getCopyToReg.*getEntryNode


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