[PATCH] D18097: [Power9] basic support for Power 9 direct move instructions
amehsan via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 10:34:51 PDT 2016
amehsan added inline comments.
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1247
@@ +1246,3 @@
+ def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+ "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
> If you look at the definitions in lib/Target/PowerPC/PPCRegisterInfo.td, you'll see that the register classes have a different alignment/spill size. I am not aware of any other differences.
Then I suspect which one we use in a given instruction does not really matter (given how GPRC and G8RC are related to each other on Power). If that is the only difference, (and if tablegen language allows) I think a better design would have just one register class. But the alignment of that register class should be chosen depending on whether or not "In64BitMode" predicate is on or off.
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