[PATCH] D18237: [SLPVectorizer] Change MinVecRegSize from 128 bits to 64 bits
Jongwon Lee via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 16 22:06:09 PDT 2016
JongwonLee created this revision.
JongwonLee added subscribers: llvm-commits, flyingforyou.
Herald added subscribers: mzolotukhin, aemerson.
If the target is AArch64, MinVecRegSize can be 64 (vectorized in double register) not 128 (vectorized in quad register). Thus, we can have more opportunities to vectorize as followings <2 x 32-bit data type>, <4 x 16-bit data type>, <8 x 8-bit data type>.
The exisitng option '-slp-min-reg-size' enables only one kind of MinVecRegSize. With this patch, we can try to vectorize in the range from MaxVecRegSize to MinVecRegSize.
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