[PATCH] D16888: [mips] Addition of a third operand to the instructions [d]div, [d]divu

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

With the indentation and missing predicates fixed it will LGTM


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2062-2063
@@ +2061,4 @@
+def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                   (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "div\t$rd, $rs, $rt">,
+                ISA_MIPS1_NOT_32R6_64R6;
----------------
Indentation is off by one. There are similar cases below.

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2069
@@ +2068,3 @@
+                ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                     GPR32Opnd:$rs), 0>;
----------------
The MipsInstAlias's need predicates too. Without them, the alias is still available for all targets.

Likewise below

================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2070
@@ +2069,3 @@
+def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                     GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
----------------
Indentation. The operand should align to the first one on the previous line:
  (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
             GPR32Opnd:$rs)
There are similar cases below.


http://reviews.llvm.org/D16888