[llvm] r263407 - [AMDGPU] AsmParser: remove redundant isReg checks. NFC.
Valery Pykhtin via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 13 22:01:45 PDT 2016
Author: vpykhtin
Date: Mon Mar 14 00:01:45 2016
New Revision: 263407
URL: http://llvm.org/viewvc/llvm-project?rev=263407&view=rev
Log:
[AMDGPU] AsmParser: remove redundant isReg checks. NFC.
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=263407&r1=263406&r2=263407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Mar 14 00:01:45 2016
@@ -277,11 +277,11 @@ public:
}
bool isSCSrc32() const {
- return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
+ return isInlinableImm() || isRegClass(AMDGPU::SReg_32RegClassID);
}
bool isSCSrc64() const {
- return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
+ return isInlinableImm() || isRegClass(AMDGPU::SReg_64RegClassID);
}
bool isSSrc32() const {
@@ -295,11 +295,11 @@ public:
}
bool isVCSrc32() const {
- return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
+ return isInlinableImm() || isRegClass(AMDGPU::VS_32RegClassID);
}
bool isVCSrc64() const {
- return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
+ return isInlinableImm() || isRegClass(AMDGPU::VS_64RegClassID);
}
bool isVSrc32() const {
@@ -1752,7 +1752,7 @@ static bool isVOP3(OperandVector &Operan
if (Operands.size() >= 2) {
AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
- if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
+ if (DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
return true;
}
@@ -1761,8 +1761,8 @@ static bool isVOP3(OperandVector &Operan
if (Operands.size() > 3) {
AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]);
- if (Src1Op.isReg() && (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) ||
- Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)))
+ if (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) ||
+ Src1Op.isRegClass(AMDGPU::SReg_64RegClassID))
return true;
}
return false;
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