[llvm] r263229 - [mips] MIPSR6 Instruction itineraries
Vasileios Kalintiris via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 11 05:05:06 PST 2016
Author: vkalintiris
Date: Fri Mar 11 07:05:06 2016
New Revision: 263229
URL: http://llvm.org/viewvc/llvm-project?rev=263229&view=rev
Log:
[mips] MIPSR6 Instruction itineraries
Summary: Defines instruction itineraries for common MIPSR6 instructions.
Patch by Simon Dardis.
Reviewers: vkalintiris
Subscribers: MatzeB, dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D17198
Modified:
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSchedule.td
llvm/trunk/test/CodeGen/Mips/divrem.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=263229&r1=263228&r2=263229&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Fri Mar 11 07:05:06 2016
@@ -245,47 +245,56 @@ multiclass CMP_CC_M <FIELD_CMP_FORMAT Fo
//===----------------------------------------------------------------------===//
class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd> : MipsR6Arch<instr_asm> {
+ Operand ImmOpnd, InstrItinClass itin>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins ImmOpnd:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
-class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
-class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
+class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
+ II_ADDIUPC>;
+class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
+class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd> : MipsR6Arch<instr_asm> {
+ Operand ImmOpnd, InstrItinClass itin>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
+class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;
-class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
- : MipsR6Arch<instr_asm> {
+class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin = NoItinerary>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
-class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
+class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
+class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
-class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
- : MipsR6Arch<instr_asm> {
+class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin = NoItinerary>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
+class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
class BRANCH_DESC_BASE {
bit isBranch = 1;
@@ -299,6 +308,7 @@ class BC_DESC_BASE<string instr_asm, DAG
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$offset");
bit isBarrier = 1;
+ InstrItinClass Itinerary = II_BC;
}
class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
@@ -307,6 +317,7 @@ class CMP_BC_DESC_BASE<string instr_asm,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
list<Register> Defs = [AT];
+ InstrItinClass Itinerary = II_BCCC;
}
class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
@@ -315,6 +326,7 @@ class CMP_CBR_EQNE_Z_DESC_BASE<string in
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
list<Register> Defs = [AT];
+ InstrItinClass Itinerary = II_BCCZC;
}
class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
@@ -324,6 +336,7 @@ class CMP_CBR_RT_Z_DESC_BASE<string inst
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT];
+ InstrItinClass Itinerary = II_BCCZC;
}
class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
@@ -335,6 +348,7 @@ class BAL_DESC : BC_DESC_BASE<"bal", brt
class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
bit isCall = 1;
list<Register> Defs = [RA];
+ InstrItinClass Itinerary = II_BALC;
}
class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
@@ -360,6 +374,7 @@ class COP1_BCCZ_DESC_BASE<string instr_a
dag OutOperandList = (outs);
string AsmString = instr_asm;
bit hasDelaySlot = 1;
+ InstrItinClass Itinerary = II_BC1CCZ;
}
class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
@@ -379,22 +394,25 @@ class BOVC_DESC : CMP_BC_DESC_BASE<"bo
class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
- RegisterOperand GPROpnd>
+ RegisterOperand GPROpnd,
+ InstrItinClass itin = NoItinerary>
: MipsR6Arch<opstr> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<dag> Pattern = [];
bit isTerminator = 1;
bit hasDelaySlot = 0;
+ InstrItinClass Itinerary = itin;
}
class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
- GPR32Opnd> {
+ GPR32Opnd, II_JIALC> {
bit isCall = 1;
list<Register> Defs = [RA];
}
-class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
+class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
+ GPR32Opnd, II_JIALC> {
bit isBarrier = 1;
list<Register> Defs = [AT];
}
@@ -407,33 +425,36 @@ class JR_HB_R6_DESC : JR_HB_DESC_BASE<"j
bit isBarrier=1;
}
-class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
+class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin,
SDPatternOperator Op=null_frag>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
-
+ InstrItinClass Itinerary = itin;
// This instruction doesn't trap division by zero itself. We must insert
// teq instructions as well.
bit usesCustomInserter = 1;
}
-class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
-class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
-class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
-class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
+class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
+class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
+class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
+class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
list<Register> Defs = [RA];
@@ -460,17 +481,19 @@ class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_B
}
class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin,
SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
+ InstrItinClass Itinerary = itin;
}
-class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
-class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
-class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
-class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
+class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
+class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
+class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
+class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
@@ -494,23 +517,26 @@ class SELEQNE_Z_DESC_BASE<string instr_a
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = II_SELCCZ;
}
class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
-class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
+class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
+ InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [];
string Constraints = "$fd_in = $fd";
+ InstrItinClass Itinerary = itin;
}
-class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
-class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
-class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
-class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
+class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;
+class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
+class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
+class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
@@ -590,55 +616,65 @@ class SDC2_R6_DESC : COP2ST_DESC_BASE<"s
class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd> : MipsR6Arch<instr_asm> {
+ Operand ImmOpnd, InstrItinClass itin>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
list<dag> Pattern = [];
+ InstrItinClass Itinerary = itin;
}
-class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
+class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
-class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
+ InstrItinClass Itinerary = itin;
}
-class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>;
+class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
-class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin> {
dag OutOperandList = (outs GPROpnd:$dst);
dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayStore = 1;
string Constraints = "$rt = $dst";
+ InstrItinClass Itinerary = itin;
}
-class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
+class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
-class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
+ InstrItinClass Itinerary = itin;
}
-class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
- CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
+class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin> :
+ CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
}
-class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
- CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
+class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ InstrItinClass itin> :
+ CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
}
-class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
-class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
+class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
+class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
class SDBBP_R6_DESC {
dag OutOperandList = (outs);
Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=263229&r1=263228&r2=263229&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Fri Mar 11 07:05:06 2016
@@ -46,32 +46,33 @@ class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPC
//
//===----------------------------------------------------------------------===//
-class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
string Constraints = "$rs = $rt";
+ InstrItinClass Itinerary = itin;
}
-class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
-class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
-class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
-class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
-class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
-class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
-class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
-class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
-class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
-class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1>;
-class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
-class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
-class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
-class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
-class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
-class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
-class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
-class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
-class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
+class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
+class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
+class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
+class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
+class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
+class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
+class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
+class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
+class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
+class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
+class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
+class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
+class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
+class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
+class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
+class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
+class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
+class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, II_LLD>;
+class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
Modified: llvm/trunk/lib/Target/Mips/MipsSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSchedule.td?rev=263229&r1=263228&r2=263229&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSchedule.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsSchedule.td Fri Mar 11 07:05:06 2016
@@ -23,24 +23,33 @@ def IIPseudo : InstrItinClass;
def II_ABS : InstrItinClass;
def II_ADDI : InstrItinClass;
def II_ADDIU : InstrItinClass;
+def II_ADDIUPC : InstrItinClass;
def II_ADDU : InstrItinClass;
def II_ADD_D : InstrItinClass;
def II_ADD_S : InstrItinClass;
+def II_ALIGN : InstrItinClass;
def II_AND : InstrItinClass;
def II_ANDI : InstrItinClass;
+def II_ALUIPC : InstrItinClass;
+def II_AUI : InstrItinClass;
+def II_AUIPC : InstrItinClass;
def II_B : InstrItinClass;
def II_BADDU : InstrItinClass;
def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32
+def II_BALC : InstrItinClass;
def II_BC : InstrItinClass;
def II_BC1F : InstrItinClass;
def II_BC1FL : InstrItinClass;
def II_BC1T : InstrItinClass;
def II_BC1TL : InstrItinClass;
+def II_BC1CCZ : InstrItinClass;
def II_BCC : InstrItinClass; // beq and bne
def II_BCCZ : InstrItinClass; // b[gl][et]z
+def II_BCCC : InstrItinClass; // b<cc>c
def II_BCCZAL : InstrItinClass; // bgezal and bltzal
def II_BCCZALS : InstrItinClass; // bgezals and bltzals
def II_BCCZC : InstrItinClass; // beqzc, bnezc
+def II_BITSWAP : InstrItinClass;
def II_CEIL : InstrItinClass;
def II_CFC1 : InstrItinClass;
def II_CLO : InstrItinClass;
@@ -52,6 +61,13 @@ def II_C_CC_S : InstrItinClass
def II_DADDIU : InstrItinClass;
def II_DADDU : InstrItinClass;
def II_DADD : InstrItinClass;
+def II_DAHI : InstrItinClass;
+def II_DATI : InstrItinClass;
+def II_DAUI : InstrItinClass;
+def II_DALIGN : InstrItinClass;
+def II_DBITSWAP : InstrItinClass;
+def II_DCLO : InstrItinClass;
+def II_DCLZ : InstrItinClass;
def II_DDIV : InstrItinClass;
def II_DDIVU : InstrItinClass;
def II_DIV : InstrItinClass;
@@ -60,7 +76,12 @@ def II_DIV_D : InstrItinClass
def II_DIV_S : InstrItinClass;
def II_DMFC1 : InstrItinClass;
def II_DMTC1 : InstrItinClass;
+def II_DMOD : InstrItinClass;
+def II_DMODU : InstrItinClass;
+def II_DMUH : InstrItinClass;
+def II_DMUHU : InstrItinClass;
def II_DMUL : InstrItinClass;
+def II_DMULU : InstrItinClass;
def II_DMULT : InstrItinClass;
def II_DMULTU : InstrItinClass;
def II_DROTR : InstrItinClass;
@@ -87,6 +108,8 @@ def II_JALR : InstrItinClass
def II_JALRC : InstrItinClass;
def II_JALRS : InstrItinClass;
def II_JALS : InstrItinClass;
+def II_JIC : InstrItinClass;
+def II_JIALC : InstrItinClass;
def II_JR : InstrItinClass;
def II_JRADDIUSP : InstrItinClass;
def II_JRC : InstrItinClass;
@@ -99,6 +122,7 @@ def II_LD : InstrItinClass
def II_LDC1 : InstrItinClass;
def II_LDL : InstrItinClass;
def II_LDR : InstrItinClass;
+def II_LDPC : InstrItinClass;
def II_LDXC1 : InstrItinClass;
def II_LH : InstrItinClass;
def II_LHE : InstrItinClass;
@@ -111,17 +135,27 @@ def II_LWE : InstrItinClass
def II_LWC1 : InstrItinClass;
def II_LWL : InstrItinClass;
def II_LWLE : InstrItinClass;
+def II_LWPC : InstrItinClass;
def II_LWR : InstrItinClass;
def II_LWRE : InstrItinClass;
def II_LWU : InstrItinClass;
+def II_LWUPC : InstrItinClass;
def II_LWXC1 : InstrItinClass;
+def II_LL : InstrItinClass;
+def II_LLD : InstrItinClass;
+def II_LSA : InstrItinClass;
+def II_DLSA : InstrItinClass;
def II_MADD : InstrItinClass;
def II_MADDU : InstrItinClass;
def II_MADD_D : InstrItinClass;
def II_MADD_S : InstrItinClass;
+def II_MADDF_D : InstrItinClass;
+def II_MADDF_S : InstrItinClass;
def II_MFC1 : InstrItinClass;
def II_MFHC1 : InstrItinClass;
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
+def II_MOD : InstrItinClass;
+def II_MODU : InstrItinClass;
def II_MOVF : InstrItinClass;
def II_MOVF_D : InstrItinClass;
def II_MOVF_S : InstrItinClass;
@@ -140,10 +174,15 @@ def II_MSUB : InstrItinClass
def II_MSUBU : InstrItinClass;
def II_MSUB_D : InstrItinClass;
def II_MSUB_S : InstrItinClass;
+def II_MSUBF_D : InstrItinClass;
+def II_MSUBF_S : InstrItinClass;
def II_MTC1 : InstrItinClass;
def II_MTHC1 : InstrItinClass;
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
def II_MUL : InstrItinClass;
+def II_MUH : InstrItinClass;
+def II_MUHU : InstrItinClass;
+def II_MULU : InstrItinClass;
def II_MULT : InstrItinClass;
def II_MULTU : InstrItinClass;
def II_MUL_D : InstrItinClass;
@@ -163,6 +202,8 @@ def II_ROTR : InstrItinClass
def II_ROTRV : InstrItinClass;
def II_ROUND : InstrItinClass;
def II_SAVE : InstrItinClass;
+def II_SC : InstrItinClass;
+def II_SCD : InstrItinClass;
def II_SB : InstrItinClass;
def II_SBE : InstrItinClass;
def II_SD : InstrItinClass;
@@ -172,6 +213,7 @@ def II_SDR : InstrItinClass
def II_SDXC1 : InstrItinClass;
def II_SEB : InstrItinClass;
def II_SEH : InstrItinClass;
+def II_SELCCZ : InstrItinClass;
def II_SEQ_SNE : InstrItinClass; // seq and sne
def II_SEQI_SNEI : InstrItinClass; // seqi and snei
def II_SH : InstrItinClass;
@@ -210,9 +252,15 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_ALIGN , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_BITSWAP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
@@ -226,6 +274,15 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DALIGN , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DAHI , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DATI , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DAUI , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DBITSWAP , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
@@ -259,11 +316,16 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_LH , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
+ InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>,
+ InstrItinData<II_LWUPC , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LD , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>,
+ InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>,
+ InstrItinData<II_LL , [InstrStage<3, [ALU]>]>,
+ InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>,
InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
InstrItinData<II_SB , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
@@ -274,16 +336,22 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_SELCCZ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
InstrItinData<II_B , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_BALC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>,
@@ -295,22 +363,32 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>,
InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_JIC , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_JIALC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_JR , [InstrStage<1, [ALU]>]>,
InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_DMULU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
+ InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>,
+ InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>,
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
+ InstrItinData<II_MUH , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_MUHU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
+ InstrItinData<II_MULU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
@@ -342,18 +420,24 @@ def MipsGenericItineraries : ProcessorIt
InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>,
InstrItinData<II_MUL_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_MADD_S , [InstrStage<7, [ALU]>]>,
+ InstrItinData<II_MADDF_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>,
+ InstrItinData<II_MSUBF_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>,
InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
+ InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
+ InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
+ InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
+ InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>,
InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
Modified: llvm/trunk/test/CodeGen/Mips/divrem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/divrem.ll?rev=263229&r1=263228&r2=263229&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/divrem.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/divrem.ll Fri Mar 11 07:05:06 2016
@@ -152,20 +152,20 @@ entry:
; ACC64: mfhi $[[R0:[0-9]+]]
; ACC64: sw $[[R0]], 0(${{[0-9]+}})
-; GPR32: mod $[[R0:[0-9]+]], $4, $5
+; GPR32-DAG: div $2, $4, $5
; GPR32-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR32: sw $[[R0]], 0(${{[0-9]+}})
-; GPR32-DAG: div $2, $4, $5
+; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5
; GPR32-TRAP: teq $5, $zero, 7
+; GPR32: sw $[[R0]], 0(${{[0-9]+}})
-; GPR64: mod $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG: div $2, $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR64: sw $[[R0]], 0(${{[0-9]+}})
-; GPR64-DAG: div $2, $4, $5
+; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
+; GPR64: sw $[[R0]], 0(${{[0-9]+}})
; ALL: .end sdivrem1
@@ -193,21 +193,21 @@ entry:
; ACC64: mfhi $[[R0:[0-9]+]]
; ACC64: sw $[[R0]], 0(${{[0-9]+}})
-; GPR32: modu $[[R0:[0-9]+]], $4, $5
+; GPR32-DAG: divu $2, $4, $5
; GPR32-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR32: sw $[[R0]], 0(${{[0-9]+}})
-; GPR32-DAG: divu $2, $4, $5
+; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5
; GPR32-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
+; GPR32: sw $[[R0]], 0(${{[0-9]+}})
-; GPR64: modu $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG: divu $2, $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR64: sw $[[R0]], 0(${{[0-9]+}})
-; GPR64-DAG: divu $2, $4, $5
+; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
+; GPR64: sw $[[R0]], 0(${{[0-9]+}})
; ALL: .end udivrem1
@@ -335,14 +335,14 @@ entry:
; ACC64: mfhi $[[R0:[0-9]+]]
; ACC64: sd $[[R0]], 0(${{[0-9]+}})
-; GPR64: dmod $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG: ddiv $2, $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR64: sd $[[R0]], 0(${{[0-9]+}})
-; GPR64-DAG: ddiv $2, $4, $5
+; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
+; GPR64: sd $[[R0]], 0(${{[0-9]+}})
; ALL: .end sdivrem2
@@ -370,14 +370,14 @@ entry:
; ACC64: mfhi $[[R0:[0-9]+]]
; ACC64: sd $[[R0]], 0(${{[0-9]+}})
-; GPR64: dmodu $[[R0:[0-9]+]], $4, $5
+; GPR64-DAG: ddivu $2, $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
-; GPR64: sd $[[R0]], 0(${{[0-9]+}})
-; GPR64-DAG: ddivu $2, $4, $5
+; GPR64: dmodu $[[R0:[0-9]+]], $4, $5
; GPR64-TRAP: teq $5, $zero, 7
; NOCHECK-NOT: teq
+; GPR64: sd $[[R0]], 0(${{[0-9]+}})
; ALL: .end udivrem2
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=263229&r1=263228&r2=263229&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Fri Mar 11 07:05:06 2016
@@ -169,12 +169,12 @@ entry:
; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
; 32R1-R5: addu $2, $[[T0]], $[[T1]]
- ; 32R6: mul $[[T0:[0-9]+]], $5, $6
- ; 32R6: muhu $[[T1:[0-9]+]], $5, $7
- ; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
- ; 32R6: mul $[[T2:[0-9]+]], $4, $7
- ; 32R6: addu $2, $[[T0]], $[[T2]]
- ; 32R6: mul $3, $5, $7
+ ; 32R6-DAG: mul $3, $5, $7
+ ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7
+ ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6
+ ; 32R6: muhu $[[T2:[0-9]+]], $5, $7
+ ; 32R6: addu $[[T1]], $[[T2]], $[[T1]]
+ ; 32R6: addu $2, $[[T1]], $[[T0]]
; M4: dmult $4, $5
; M4: mflo $2
@@ -204,12 +204,12 @@ entry:
; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
- ; 64R6: dmul $[[T0:[0-9]+]], $5, $6
- ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7
- ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
- ; 64R6: dmul $[[T3:[0-9]+]], $4, $7
- ; 64R6: daddu $2, $[[T2]], $[[T3]]
- ; 64R6: dmul $3, $5, $7
+ ; 64R6-DAG: dmul $3, $5, $7
+ ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
+ ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
+ ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
+ ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 64R6: daddu $2, $[[T1]], $[[T0]]
%r = mul i128 %a, %b
ret i128 %r
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