[llvm] r263108 - [AMDGPU] Fix SMEM instructions encoding/operand namings
Valery Pykhtin via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 10 05:06:09 PST 2016
Author: vpykhtin
Date: Thu Mar 10 07:06:08 2016
New Revision: 263108
URL: http://llvm.org/viewvc/llvm-project?rev=263108&view=rev
Log:
[AMDGPU] Fix SMEM instructions encoding/operand namings
Differential Revision: http://reviews.llvm.org/D17651
Added:
llvm/trunk/test/MC/Disassembler/AMDGPU/smrd_vi.txt
Modified:
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td
llvm/trunk/test/MC/AMDGPU/smrd.s
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Thu Mar 10 07:06:08 2016
@@ -66,10 +66,12 @@ DECODE_OPERAND(VReg_64)
DECODE_OPERAND(VReg_96)
DECODE_OPERAND(VReg_128)
+DECODE_OPERAND(SGPR_32)
DECODE_OPERAND(SReg_32)
DECODE_OPERAND(SReg_64)
DECODE_OPERAND(SReg_128)
DECODE_OPERAND(SReg_256)
+DECODE_OPERAND(SReg_512)
#define GET_SUBTARGETINFO_ENUM
#include "AMDGPUGenSubtargetInfo.inc"
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Thu Mar 10 07:06:08 2016
@@ -229,9 +229,7 @@ class SOPPe <bits<7> op> : Enc32 {
class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
bits<7> sdst;
bits<7> sbase;
- bits<8> offset;
- let Inst{7-0} = offset;
let Inst{8} = imm;
let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst;
@@ -239,6 +237,18 @@ class SMRDe <bits<5> op, bits<1> imm> :
let Inst{31-27} = 0x18; //encoding
}
+class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
+ bits<8> offset;
+ let Inst{7-0} = offset;
+}
+
+class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
+ bits<8> soff;
+ let Inst{7-0} = soff;
+}
+
+
+
class SMRD_IMMe_ci <bits<5> op> : Enc64 {
bits<7> sdst;
bits<7> sbase;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Thu Mar 10 07:06:08 2016
@@ -1083,53 +1083,88 @@ class SMRD_Pseudo <string opName, dag ou
let isCodeGenOnly = 1;
}
-class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
- string asm> :
+class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
+ string asm> :
SMRD <outs, ins, asm, []>,
- SMRDe <op, imm>,
+ SMRD_IMMe <op>,
SIMCInstr<opName, SISubtarget.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
-class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
- string asm, list<dag> pattern = []> :
+class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
+ string asm> :
+ SMRD <outs, ins, asm, []>,
+ SMRD_SOFFe <op>,
+ SIMCInstr<opName, SISubtarget.SI> {
+ let AssemblerPredicates = [isSICI];
+ let DecoderNamespace = "SICI";
+ let DisableDecoder = DisableSIDecoder;
+}
+
+
+class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
+ string asm, list<dag> pattern = []> :
SMRD <outs, ins, asm, pattern>,
- SMEMe_vi <op, imm>,
+ SMEM_IMMe_vi <op>,
SIMCInstr<opName, SISubtarget.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
-multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
+class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
+ string asm, list<dag> pattern = []> :
+ SMRD <outs, ins, asm, pattern>,
+ SMEM_SOFFe_vi <op>,
+ SIMCInstr<opName, SISubtarget.VI> {
+ let AssemblerPredicates = [isVI];
+ let DecoderNamespace = "VI";
+ let DisableDecoder = DisableVIDecoder;
+}
+
+
+multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
string asm, list<dag> pattern> {
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
- def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
+ def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>;
// glc is only applicable to scalar stores, which are not yet
// implemented.
let glc = 0 in {
- def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
+ def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>;
+ }
+}
+
+multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins,
+ string asm, list<dag> pattern> {
+
+ def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
+
+ def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>;
+
+ // glc is only applicable to scalar stores, which are not yet
+ // implemented.
+ let glc = 0 in {
+ def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>;
}
}
multiclass SMRD_Special <smrd op, string opName, dag outs,
+ int sdst_ = ?,
string opStr = "",
list<dag> pattern = []> {
let hasSideEffects = 1 in {
def "" : SMRD_Pseudo <opName, outs, (ins), pattern>;
- let sbase = 0, offset = 0 in {
- let sdst = 0 in {
- def _si : SMRD_Real_si <op.SI, opName, 0, outs, (ins), opName#opStr>;
- }
+ let sbase = 0, soff = 0, sdst = sdst_ in {
+ def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>;
- let glc = 0, sdata = 0 in {
- def _vi : SMRD_Real_vi <op.VI, opName, 0, outs, (ins), opName#opStr>;
+ let glc = 0 in {
+ def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>;
}
}
}
@@ -1138,51 +1173,50 @@ multiclass SMRD_Special <smrd op, string
multiclass SMRD_Inval <smrd op, string opName,
SDPatternOperator node> {
let mayStore = 1 in {
- defm : SMRD_Special<op, opName, (outs), "", [(node)]>;
+ defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>;
}
}
class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
- SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
+ SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> {
let hasSideEffects = 1;
let mayStore = 1;
let sbase = 0;
- let sdata = 0;
+ let sdst = 0;
let glc = 0;
- let offset = 0;
+ let soff = 0;
}
class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> :
- SMRD_Real_vi<op, opName, 0, (outs SReg_64:$dst), (ins),
- opName#" $dst", [(set i64:$dst, (node))]> {
+ SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
+ opName#" $sdst", [(set i64:$sdst, (node))]> {
let hasSideEffects = 1;
let mayStore = ?;
let mayLoad = ?;
let sbase = 0;
- let sdata = 0;
let glc = 0;
- let offset = 0;
+ let soff = 0;
}
multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
RegisterClass dstClass> {
- defm _IMM : SMRD_m <
- op, opName#"_IMM", 1, (outs dstClass:$dst),
+ defm _IMM : SMRD_IMM_m <
+ op, opName#"_IMM", (outs dstClass:$sdst),
(ins baseClass:$sbase, smrd_offset:$offset),
- opName#" $dst, $sbase, $offset", []
+ opName#" $sdst, $sbase, $offset", []
>;
def _IMM_ci : SMRD <
- (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
- opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
+ (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
+ opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
}
- defm _SGPR : SMRD_m <
- op, opName#"_SGPR", 0, (outs dstClass:$dst),
+ defm _SGPR : SMRD_SOFF_m <
+ op, opName#"_SGPR", (outs dstClass:$sdst),
(ins baseClass:$sbase, SReg_32:$soff),
- opName#" $dst, $sbase, $soff", []
+ opName#" $sdst, $sbase, $soff", []
>;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Thu Mar 10 07:06:08 2016
@@ -94,7 +94,7 @@ let mayStore = ? in {
// Pat. Each considers the other contradictory.
defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
- (outs SReg_64:$dst), " $dst", [(set i64:$dst, (int_amdgcn_s_memtime))]
+ (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
>;
}
Modified: llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td Thu Mar 10 07:06:08 2016
@@ -91,19 +91,27 @@ class MTBUFe_vi <bits<4> op> : Enc64 {
class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
bits<7> sbase;
- bits<7> sdata;
+ bits<7> sdst;
bits<1> glc;
- bits<20> offset;
let Inst{5-0} = sbase{6-1};
- let Inst{12-6} = sdata;
+ let Inst{12-6} = sdst;
let Inst{16} = glc;
let Inst{17} = imm;
let Inst{25-18} = op;
let Inst{31-26} = 0x30; //encoding
+}
+
+class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
+ bits<20> offset;
let Inst{51-32} = offset;
}
+class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
+ bits<20> soff;
+ let Inst{51-32} = soff;
+}
+
class VOP3a_vi <bits<10> op> : Enc64 {
bits<2> src0_modifiers;
bits<9> src0;
Modified: llvm/trunk/test/MC/AMDGPU/smrd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=263108&r1=263107&r2=263108&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smrd.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smrd.s Thu Mar 10 07:06:08 2016
@@ -1,21 +1,27 @@
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=VI %s
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s --check-prefix=NOSI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOVI
+
//===----------------------------------------------------------------------===//
// Offset Handling
//===----------------------------------------------------------------------===//
s_load_dword s1, s[2:3], 0xfc
// GCN: s_load_dword s1, s[2:3], 0xfc ; encoding: [0xfc,0x83,0x00,0xc0]
+// VI: s_load_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x02,0xc0,0xfc,0x00,0x00,0x00]
s_load_dword s1, s[2:3], 0xff
// GCN: s_load_dword s1, s[2:3], 0xff ; encoding: [0xff,0x83,0x00,0xc0]
+// VI: s_load_dword s1, s[2:3], 0xff ; encoding: [0x41,0x00,0x02,0xc0,0xff,0x00,0x00,0x00]
s_load_dword s1, s[2:3], 0x100
// NOSI: error: instruction not supported on this GPU
+// NOVI: error: instruction not supported on this GPU
// CI: s_load_dword s1, s[2:3], 0x100 ; encoding: [0xff,0x82,0x00,0xc0,0x00,0x01,0x00,0x00]
//===----------------------------------------------------------------------===//
@@ -24,49 +30,65 @@ s_load_dword s1, s[2:3], 0x100
s_load_dword s1, s[2:3], 1
// GCN: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
+// VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
s_load_dword s1, s[2:3], s4
// GCN: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
+// VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx2 s[2:3], s[2:3], 1
// GCN: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
+// VI: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
s_load_dwordx2 s[2:3], s[2:3], s4
// GCN: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
+// VI: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx4 s[4:7], s[2:3], 1
// GCN: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
+// VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
s_load_dwordx4 s[4:7], s[2:3], s4
// GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
+// VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx4 s[100:103], s[2:3], s4
// GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
+// NOVI: error: invalid operand for instruction
s_load_dwordx8 s[8:15], s[2:3], 1
// GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
+// VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
s_load_dwordx8 s[8:15], s[2:3], s4
// GCN: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0]
+// VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx8 s[96:103], s[2:3], s4
// GCN: s_load_dwordx8 s[96:103], s[2:3], s4 ; encoding: [0x04,0x02,0xf0,0xc0]
+// NOVI: error: invalid operand for instruction
s_load_dwordx16 s[16:31], s[2:3], 1
// GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
+// VI: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x04,0x12,0xc0,0x01,0x00,0x00,0x00]
s_load_dwordx16 s[16:31], s[2:3], s4
// GCN: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1]
+// VI: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x01,0x04,0x10,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx16 s[88:103], s[2:3], s4
// GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
+// NOVI: error: invalid operand for instruction
s_dcache_inv
// GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
+// VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
s_dcache_inv_vol
// CI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x40,0xc7]
// NOSI: error: instruction not supported on this GPU
+// VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
s_memtime s[0:1]
// GCN: s_memtime s[0:1] ; encoding: [0x00,0x00,0x80,0xc7]
+// VI: s_memtime s[0:1] ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]
Added: llvm/trunk/test/MC/Disassembler/AMDGPU/smrd_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/smrd_vi.txt?rev=263108&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/smrd_vi.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/smrd_vi.txt Thu Mar 10 07:06:08 2016
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
+0x41 0x00 0x02 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
+0x41 0x00 0x00 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
+0x81 0x00 0x06 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
+0x81 0x00 0x04 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x01 0x0a 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x01 0x08 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x02 0x0e 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x02 0x0c 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x04,0x12,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x04 0x12 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x01,0x04,0x10,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x04 0x10 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x80 0xc0 0x00 0x00 0x00 0x00
+
+# VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x88 0xc0 0x00 0x00 0x00 0x00
+
+# VI: s_memtime s[0:1] ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x90 0xc0 0x00 0x00 0x00 0x00
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