[llvm] r262903 - [WebAssembly] Update for spec change from tableswitch to br_table.
Dan Gohman via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 7 19:18:12 PST 2016
Author: djg
Date: Mon Mar 7 21:18:12 2016
New Revision: 262903
URL: http://llvm.org/viewvc/llvm-project?rev=262903&view=rev
Log:
[WebAssembly] Update for spec change from tableswitch to br_table.
Also note that the operand order changed; the default label is now listed
after the regular labels.
Modified:
llvm/trunk/lib/Target/WebAssembly/README.txt
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll
llvm/trunk/test/CodeGen/WebAssembly/switch.ll
Modified: llvm/trunk/lib/Target/WebAssembly/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/README.txt?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/README.txt (original)
+++ llvm/trunk/lib/Target/WebAssembly/README.txt Mon Mar 7 21:18:12 2016
@@ -32,7 +32,7 @@ Interesting work that remains to be done
//===---------------------------------------------------------------------===//
-Br, br_if, and tableswitch instructions can support having a value on the
+Br, br_if, and br_table instructions can support having a value on the
expression stack across the jump (sometimes). We should (a) model this, and
(b) extend the stackifier to utilize it.
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISD.def Mon Mar 7 21:18:12 2016
@@ -20,6 +20,6 @@ HANDLE_NODETYPE(RETURN)
HANDLE_NODETYPE(ARGUMENT)
HANDLE_NODETYPE(Wrapper)
HANDLE_NODETYPE(BR_IF)
-HANDLE_NODETYPE(TABLESWITCH)
+HANDLE_NODETYPE(BR_TABLE)
// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Mon Mar 7 21:18:12 2016
@@ -631,7 +631,7 @@ SDValue WebAssemblyTargetLowering::Lower
SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) const {
// There's no need for a Wrapper node because we always incorporate a jump
- // table operand into a TABLESWITCH instruction, rather than ever
+ // table operand into a BR_TABLE instruction, rather than ever
// materializing it in a register.
const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
@@ -653,15 +653,15 @@ SDValue WebAssemblyTargetLowering::Lower
MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
+ // Add an operand for each case.
+ for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
+
// TODO: For now, we just pick something arbitrary for a default case for now.
// We really want to sniff out the guard and put in the real default case (and
// delete the guard).
Ops.push_back(DAG.getBasicBlock(MBBs[0]));
- // Add an operand for each case.
- for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
-
- return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
+ return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
}
SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrControl.td Mon Mar 7 21:18:12 2016
@@ -39,20 +39,20 @@ def : Pat<(brcond (i32 (seteq I32:$cond,
let Defs = [ARGUMENTS] in {
// TODO: SelectionDAG's lowering insists on using a pointer as the index for
-// jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode
+// jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
// currently.
// Set TSFlags{0} to 1 to indicate that the variable_ops are immediates.
// Set TSFlags{1} to 1 to indicate that the immediates represent labels.
let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
-def TABLESWITCH_I32 : I<(outs), (ins I32:$index, bb_op:$default, variable_ops),
- [(WebAssemblytableswitch I32:$index, bb:$default)],
- "tableswitch\t$index, $default"> {
+def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
+ [(WebAssemblybr_table I32:$index)],
+ "br_table \t$index"> {
let TSFlags{0} = 1;
let TSFlags{1} = 1;
}
-def TABLESWITCH_I64 : I<(outs), (ins I64:$index, bb_op:$default, variable_ops),
- [(WebAssemblytableswitch I64:$index, bb:$default)],
- "tableswitch\t$index, $default"> {
+def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
+ [(WebAssemblybr_table I64:$index)],
+ "br_table \t$index"> {
let TSFlags{0} = 1;
let TSFlags{1} = 1;
}
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td Mon Mar 7 21:18:12 2016
@@ -30,7 +30,7 @@ def SDT_WebAssemblyCallSeqEnd :
SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
-def SDT_WebAssemblyTableswitch : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
+def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
@@ -52,9 +52,9 @@ def WebAssemblycall0 : SDNode<"WebAssemb
def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
SDT_WebAssemblyCall1,
[SDNPHasChain, SDNPVariadic]>;
-def WebAssemblytableswitch : SDNode<"WebAssemblyISD::TABLESWITCH",
- SDT_WebAssemblyTableswitch,
- [SDNPHasChain, SDNPVariadic]>;
+def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
+ SDT_WebAssemblyBrTable,
+ [SDNPHasChain, SDNPVariadic]>;
def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
SDT_WebAssemblyArgument>;
def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
Modified: llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/cfg-stackify.ll Mon Mar 7 21:18:12 2016
@@ -895,7 +895,7 @@ end:
; CHECK-NOT: block
; CHECK: br_if 5, {{[^,]+}}{{$}}
; CHECK-NOT: block
-; CHECK: tableswitch {{[^,]+}}, 0, 0, 1, 5, 2, 4{{$}}
+; CHECK: br_table {{[^,]+}}, 0, 1, 5, 2, 4, 0{{$}}
; CHECK-NEXT: .LBB19_5:
; CHECK-NEXT: end_loop{{$}}
; CHECK-NEXT: end_loop{{$}}
@@ -919,7 +919,7 @@ end:
; OPT-NOT: block
; OPT: br_if 5, {{[^,]+}}{{$}}
; OPT-NOT: block
-; OPT: tableswitch {{[^,]+}}, 0, 0, 1, 5, 2, 4{{$}}
+; OPT: br_table {{[^,]+}}, 0, 1, 5, 2, 4, 0{{$}}
; OPT-NEXT: .LBB19_5:
; OPT-NEXT: end_loop{{$}}
; OPT-NEXT: end_loop{{$}}
Modified: llvm/trunk/test/CodeGen/WebAssembly/switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/switch.ll?rev=262903&r1=262902&r2=262903&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/switch.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/switch.ll Mon Mar 7 21:18:12 2016
@@ -21,7 +21,7 @@ declare void @foo5()
; CHECK: block{{$}}
; CHECK: block{{$}}
; CHECK: block{{$}}
-; CHECK: tableswitch {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5{{$}}
+; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
; CHECK: .LBB0_2:
; CHECK: call foo0 at FUNCTION{{$}}
; CHECK: .LBB0_3:
@@ -101,7 +101,7 @@ sw.epilog:
; CHECK: block{{$}}
; CHECK: block{{$}}
; CHECK: block{{$}}
-; CHECK: tableswitch {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5{{$}}
+; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
; CHECK: .LBB1_2:
; CHECK: call foo0 at FUNCTION{{$}}
; CHECK: .LBB1_3:
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