[PATCH] D17868: Allow target-specific postprocessing of the schedule DAG

[Krzysztof Parzyszek via llvm-commits]

kparzysz created this revision.
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This would allow a target to perform final customizations of the scheduling graph after its construction.

On Hexagon we use this (in our local code) to remove output dependencies on the "overflow" bit of the USR (user status register).  Normally, having an output dependence on a register would prevent instructions from being reordered, or from being packetized together, but this bit is special: it is "sticky" and so two definitions amount to an "or" of the two.  In that sense, any output dependency on the overflow is legal to ignore for the purpose of scheduling.  Also, the architecture allows two instructions potentially setting that bit to be packetized together.

Another use for this would be to tweak instruction latencies, depending on contextual information.

On Hexagon, there is also this long-standing issue, which could be addressed through this kind of postprocessing (although it is not handled at the time):
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20130513/174058.html


Repository:
  rL LLVM

http://reviews.llvm.org/D17868

Files:
  include/llvm/Target/TargetSubtargetInfo.h
  lib/CodeGen/ScheduleDAGInstrs.cpp

Index: lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- lib/CodeGen/ScheduleDAGInstrs.cpp
+++ lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -1091,6 +1091,8 @@
   Uses.clear();
   CurrentVRegDefs.clear();
   CurrentVRegUses.clear();
+
+  ST.postprocessSchedGraph(*this);
 }
 
 raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
Index: include/llvm/Target/TargetSubtargetInfo.h
===================================================================
--- include/llvm/Target/TargetSubtargetInfo.h
+++ include/llvm/Target/TargetSubtargetInfo.h
@@ -25,6 +25,7 @@
 class DataLayout;
 class MachineFunction;
 class MachineInstr;
+class ScheduleDAGInstrs;
 class SDep;
 class SUnit;
 class TargetFrameLowering;
@@ -154,6 +155,9 @@
   // dependency.
   virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
 
+  // \brief Perform target-specific postprocessing of the schedule graph.
+  virtual void postprocessSchedGraph(ScheduleDAGInstrs &DAG) const {}
+
   // For use with PostRAScheduling: get the anti-dependence breaking that should
   // be performed before post-RA scheduling.
   virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }


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