[PATCH] D17747: TableGen: Check scheduling models for completeness

[Andrew Trick via llvm-commits]

atrick added a comment.

Thanks Matthias. If you mark the model complete, won't tablegen give you a list of all unimplemented opcodes without even passing any debug flags to tablgen?

Can you just wrap the whole list of unsupported instruction like this?

let Unsupported = 1 {

  def : InstRW...

You can also provide a comma separated list of opcode names or regexes:

def : InstRW<[], (instrs "A", B", ...)>

You don't need a separate InstRW for each.

I think this is a pretty trivial copy-paste step and agree it's better than the dynamic check.


Repository:
  rL LLVM

http://reviews.llvm.org/D17747