[PATCH] D16110: [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic

[Chuang-Yu Cheng via llvm-commits]

cycheng added inline comments.

================
Comment at: lib/Target/PowerPC/README_P9.txt:4
@@ +3,3 @@
+TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
+
+Altivec:
----------------
nemanjai wrote:
> Note: A register class for fp128 needs to be defined or we need to allow that type in vrrc.
> 
> I think either is fine since the ABI specifies the same vector registers for passing vectors and fp128 parameters.
If we allow it in vrrc, then I should add 'f128' in "def VRRC", right?


```
// PPCRegisterInfo.td
def VRRC : RegisterClass<"PPC", [ **f128**, v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
```


http://reviews.llvm.org/D16110