[PATCH] D17725: [mips] Range check uimm16_64

[Daniel Sanders via llvm-commits]

dsanders created this revision.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
dsanders added a dependency: D17723: [mips] Simplify ordering of range checked immediate classes..
Herald added a subscriber: dsanders.

Depends on D17723

http://reviews.llvm.org/D17725

Files:
  lib/Target/Mips/MipsInstrInfo.td
  test/MC/Mips/mips64r2/invalid.s

Index: test/MC/Mips/mips64r2/invalid.s
===================================================================
--- test/MC/Mips/mips64r2/invalid.s
+++ test/MC/Mips/mips64r2/invalid.s
@@ -6,6 +6,8 @@
 
         .text
         .set noreorder
+        andi $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
+        andi $2, $3, 65536   # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
         cache -1, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         cache 32, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         # FIXME: Check various 'pos + size' constraints on dext*
@@ -56,6 +58,8 @@
         ins $2, $3, 32, 1    # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         jalr.hb $31          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+        ori $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
+        ori $2, $3, 65536    # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         sll $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
@@ -66,3 +70,5 @@
         sra $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         rotr $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
         rotr $2, $3, 32      # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
+        xori $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
+        xori $2, $3, 65536   # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -635,7 +635,7 @@
 
 foreach I = {16} in
   def uimm # I : Operand<i32> {
-    let PrintMethod = "printUImm<16>";
+    let PrintMethod = "printUImm<" # I # ">";
     let ParserMatchClass =
         !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");
   }
@@ -649,16 +649,17 @@
 
 foreach I = {5} in
   def uimm # I # _64 : Operand<i64> {
-    let PrintMethod = "printUImm<5>";
+    let PrintMethod = "printUImm<" # I # ">";
     let ParserMatchClass =
         !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
   }
 
-def uimm16_64 : Operand<i64> {
-  let PrintMethod = "printUImm<16>";
-  let ParserMatchClass =
-      !cast<AsmOperandClass>("UImm16AsmOperandClass");
-}
+foreach I = {16} in
+  def uimm # I # _64 : Operand<i64> {
+    let PrintMethod = "printUImm<" # I # ">";
+    let ParserMatchClass =
+        !cast<AsmOperandClass>("UImm" # I # "AsmOperandClass");
+  }
 
 // Like uimm16_64 but coerces simm16 to uimm16.
 def uimm16_64_relaxed : Operand<i64> {


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