[PATCH] D17373: [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated.

[Milena Vujosevic Janicic via llvm-commits]

milena.vujosevic.janicic updated this revision to Diff 49369.
milena.vujosevic.janicic added a comment.

I put MicroMipsR6Inst16 on POOL16C_OR16_XOR16_FM_MMR6, as you suggested.

The test-case you suggested would not work since it would always generate right OR16_MM instruction. However, I managed to simplify a bit the test case used last time.

The test case you suggested does not trigger this bug due to the way FastISel functions. It always first calls method FastISel::selectOperator which can do fast instruction selection for a small set of operators. Then,  if selectOperator fails, FastISel calls MipsFastISel::fastSelectInstruction which checks if the architecture for which the code is generated is supported. If FastISel fails for one instruction, it does not continue trying for other instructions in that basic block. It selects instructions in reverse order.

In the test-case you suggested, FastISel tries to select an instruction for RET by selectOperator method and it fails. Then it tries to select an instruction by fastSelectInstruction, which again fails since microMips is not supported architecture, and then FastISel stops and instruction selection is continued in a normal way (and there is no bug).

In the test-case suggested in this patch, all instructions before OR are selected by selectOperator method, and then this method selects (wrong) OR16_MMR6 instruction.


http://reviews.llvm.org/D17373

Files:
  lib/Target/Mips/MicroMips32r6InstrFormats.td
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  test/CodeGen/Mips/micromips-or16.ll

Index: test/CodeGen/Mips/micromips-or16.ll
===================================================================
--- test/CodeGen/Mips/micromips-or16.ll
+++ test/CodeGen/Mips/micromips-or16.ll
@@ -1,8 +1,37 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN:  -asm-show-inst < %s | FileCheck %s
+
+declare i32 @m(i32 signext %a)
+
+define i32 @f() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  store i32 0, i32* %retval, align 4
+  %0 = load i32, i32* %a, align 4
+  %cmp = icmp eq i32 %0, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+; CHECK-LABEL: f
+; CHECK-NOT: OR16_MMR6
+  %1 = load i32, i32* %a, align 4
+  %2 = load i32, i32* %a, align 4
+  %add = add nsw i32 %2, 1
+  %or = or i32 %1, %add
+  %call = call i32 @m(i32 signext %or)
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 0
+}
 
 define i32 @main() {
 entry:
+; CHECK-LABEL: main
+; CHECK: or16
   %retval = alloca i32, align 4
   %a = alloca i32, align 4
   %b = alloca i32, align 4
@@ -14,5 +43,3 @@
   store i32 %or, i32* %a, align 4
   ret i32 0
 }
-
-; CHECK: or16
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -828,7 +828,7 @@
 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-      MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+      MMR6Arch<"sdbbp16">;
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
Index: lib/Target/Mips/MicroMips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -751,7 +751,7 @@
   let Inst{3-0}   = 0b0000;
 }
 
-class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
   bits<3> rt;
   bits<3> rs;
 


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