[llvm] r262115 - CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Duncan P. N. Exon Smith via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 26 22:40:41 PST 2016
Author: dexonsmith
Date: Sat Feb 27 00:40:41 2016
New Revision: 262115
URL: http://llvm.org/viewvc/llvm-project?rev=262115&view=rev
Log:
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are
never null, so this cleans up the API a bit. It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).
At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
llvm/trunk/lib/CodeGen/InlineSpiller.cpp
llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
llvm/trunk/lib/CodeGen/LiveInterval.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/PHIElimination.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/RegisterPressure.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/SlotIndexes.cpp
llvm/trunk/lib/CodeGen/SplitKit.cpp
llvm/trunk/lib/CodeGen/StackColoring.cpp
llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Sat Feb 27 00:40:41 2016
@@ -145,7 +145,7 @@ extern cl::opt<bool> UseSegmentSetForPhy
/// Given a register and an instruction, adds a live segment from that
/// instruction to the end of its MBB.
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
- MachineInstr* startInst);
+ MachineInstr &startInst);
/// After removing some uses of a register, shrink its live range to just
/// the remaining uses. This method does not compute reaching defs for new
@@ -195,13 +195,13 @@ extern cl::opt<bool> UseSegmentSetForPhy
/// isNotInMIMap - returns true if the specified machine instr has been
/// removed or was never entered in the map.
- bool isNotInMIMap(const MachineInstr* Instr) const {
+ bool isNotInMIMap(const MachineInstr &Instr) const {
return !Indexes->hasIndex(Instr);
}
/// Returns the base index of the given instruction.
- SlotIndex getInstructionIndex(const MachineInstr *instr) const {
- return Indexes->getInstructionIndex(instr);
+ SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
+ return Indexes->getInstructionIndex(Instr);
}
/// Returns the instruction associated with the given index.
@@ -240,21 +240,21 @@ extern cl::opt<bool> UseSegmentSetForPhy
RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
}
- SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
+ SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
return Indexes->insertMachineInstrInMaps(MI);
}
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
MachineBasicBlock::iterator E) {
for (MachineBasicBlock::iterator I = B; I != E; ++I)
- Indexes->insertMachineInstrInMaps(I);
+ Indexes->insertMachineInstrInMaps(*I);
}
- void RemoveMachineInstrFromMaps(MachineInstr *MI) {
+ void RemoveMachineInstrFromMaps(MachineInstr &MI) {
Indexes->removeMachineInstrFromMaps(MI);
}
- void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
+ void ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
Indexes->replaceMachineInstrInMaps(MI, NewMI);
}
Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Sat Feb 27 00:40:41 2016
@@ -15,6 +15,7 @@
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
#include "llvm/ADT/GraphTraits.h"
+#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/MachineInstrBundleIterator.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Support/BranchProbability.h"
@@ -192,6 +193,13 @@ public:
reverse_instr_iterator instr_rend () { return Insts.rend(); }
const_reverse_instr_iterator instr_rend () const { return Insts.rend(); }
+ typedef iterator_range<instr_iterator> instr_range;
+ typedef iterator_range<const_instr_iterator> const_instr_range;
+ instr_range instrs() { return instr_range(instr_begin(), instr_end()); }
+ const_instr_range instrs() const {
+ return const_instr_range(instr_begin(), instr_end());
+ }
+
iterator begin() { return instr_begin(); }
const_iterator begin() const { return instr_begin(); }
iterator end () { return instr_end(); }
Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Sat Feb 27 00:40:41 2016
@@ -414,14 +414,14 @@ namespace llvm {
/// Returns true if the given machine instr is mapped to an index,
/// otherwise returns false.
- bool hasIndex(const MachineInstr *instr) const {
- return mi2iMap.count(instr);
+ bool hasIndex(const MachineInstr &instr) const {
+ return mi2iMap.count(&instr);
}
/// Returns the base index for the given instruction.
- SlotIndex getInstructionIndex(const MachineInstr *MI) const {
+ SlotIndex getInstructionIndex(const MachineInstr &MI) const {
// Instructions inside a bundle have the same number as the bundle itself.
- Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(MI));
+ Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(&MI));
assert(itr != mi2iMap.end() && "Instruction not found in maps.");
return itr->second;
}
@@ -447,8 +447,8 @@ namespace llvm {
/// getIndexBefore - Returns the index of the last indexed instruction
/// before MI, or the start index of its basic block.
/// MI is not required to have an index.
- SlotIndex getIndexBefore(const MachineInstr *MI) const {
- const MachineBasicBlock *MBB = MI->getParent();
+ SlotIndex getIndexBefore(const MachineInstr &MI) const {
+ const MachineBasicBlock *MBB = MI.getParent();
assert(MBB && "MI must be inserted inna basic block");
MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
for (;;) {
@@ -464,8 +464,8 @@ namespace llvm {
/// getIndexAfter - Returns the index of the first indexed instruction
/// after MI, or the end index of its basic block.
/// MI is not required to have an index.
- SlotIndex getIndexAfter(const MachineInstr *MI) const {
- const MachineBasicBlock *MBB = MI->getParent();
+ SlotIndex getIndexAfter(const MachineInstr &MI) const {
+ const MachineBasicBlock *MBB = MI.getParent();
assert(MBB && "MI must be inserted inna basic block");
MachineBasicBlock::const_iterator I = MI, E = MBB->end();
for (;;) {
@@ -577,25 +577,25 @@ namespace llvm {
/// If Late is set and there are null indexes between mi's neighboring
/// instructions, create the new index after the null indexes instead of
/// before them.
- SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool Late = false) {
- assert(!mi->isInsideBundle() &&
+ SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
+ assert(!MI.isInsideBundle() &&
"Instructions inside bundles should use bundle start's slot.");
- assert(mi2iMap.find(mi) == mi2iMap.end() && "Instr already indexed.");
+ assert(mi2iMap.find(&MI) == mi2iMap.end() && "Instr already indexed.");
// Numbering DBG_VALUE instructions could cause code generation to be
// affected by debug information.
- assert(!mi->isDebugValue() && "Cannot number DBG_VALUE instructions.");
+ assert(!MI.isDebugValue() && "Cannot number DBG_VALUE instructions.");
- assert(mi->getParent() != nullptr && "Instr must be added to function.");
+ assert(MI.getParent() != nullptr && "Instr must be added to function.");
- // Get the entries where mi should be inserted.
+ // Get the entries where MI should be inserted.
IndexList::iterator prevItr, nextItr;
if (Late) {
- // Insert mi's index immediately before the following instruction.
- nextItr = getIndexAfter(mi).listEntry()->getIterator();
+ // Insert MI's index immediately before the following instruction.
+ nextItr = getIndexAfter(MI).listEntry()->getIterator();
prevItr = std::prev(nextItr);
} else {
- // Insert mi's index immediately after the preceding instruction.
- prevItr = getIndexBefore(mi).listEntry()->getIterator();
+ // Insert MI's index immediately after the preceding instruction.
+ prevItr = getIndexBefore(MI).listEntry()->getIterator();
nextItr = std::next(prevItr);
}
@@ -604,27 +604,27 @@ namespace llvm {
unsigned dist = ((nextItr->getIndex() - prevItr->getIndex())/2) & ~3u;
unsigned newNumber = prevItr->getIndex() + dist;
- // Insert a new list entry for mi.
+ // Insert a new list entry for MI.
IndexList::iterator newItr =
- indexList.insert(nextItr, createEntry(mi, newNumber));
+ indexList.insert(nextItr, createEntry(&MI, newNumber));
// Renumber locally if we need to.
if (dist == 0)
renumberIndexes(newItr);
SlotIndex newIndex(&*newItr, SlotIndex::Slot_Block);
- mi2iMap.insert(std::make_pair(mi, newIndex));
+ mi2iMap.insert(std::make_pair(&MI, newIndex));
return newIndex;
}
/// Remove the given machine instruction from the mapping.
- void removeMachineInstrFromMaps(MachineInstr *mi) {
+ void removeMachineInstrFromMaps(MachineInstr &MI) {
// remove index -> MachineInstr and
// MachineInstr -> index mappings
- Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);
+ Mi2IndexMap::iterator mi2iItr = mi2iMap.find(&MI);
if (mi2iItr != mi2iMap.end()) {
IndexListEntry *miEntry(mi2iItr->second.listEntry());
- assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
+ assert(miEntry->getInstr() == &MI && "Instruction indexes broken.");
// FIXME: Eventually we want to actually delete these indexes.
miEntry->setInstr(nullptr);
mi2iMap.erase(mi2iItr);
@@ -633,17 +633,17 @@ namespace llvm {
/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
/// maps used by register allocator.
- void replaceMachineInstrInMaps(MachineInstr *mi, MachineInstr *newMI) {
- Mi2IndexMap::iterator mi2iItr = mi2iMap.find(mi);
+ void replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
+ Mi2IndexMap::iterator mi2iItr = mi2iMap.find(&MI);
if (mi2iItr == mi2iMap.end())
return;
SlotIndex replaceBaseIndex = mi2iItr->second;
IndexListEntry *miEntry(replaceBaseIndex.listEntry());
- assert(miEntry->getInstr() == mi &&
+ assert(miEntry->getInstr() == &MI &&
"Mismatched instruction in index tables.");
- miEntry->setInstr(newMI);
+ miEntry->setInstr(&NewMI);
mi2iMap.erase(mi2iItr);
- mi2iMap.insert(std::make_pair(newMI, replaceBaseIndex));
+ mi2iMap.insert(std::make_pair(&NewMI, replaceBaseIndex));
}
/// Add the given MachineBasicBlock into the maps.
Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Sat Feb 27 00:40:41 2016
@@ -165,7 +165,7 @@ private:
void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = nullptr);
void analyzeSiblingValues();
- bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
+ bool hoistSpill(LiveInterval &SpillLI, MachineInstr &CopyMI);
void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
void markValueUsed(LiveInterval*, VNInfo*);
@@ -681,7 +681,7 @@ void InlineSpiller::analyzeSiblingValues
/// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
/// a spill at a better location.
-bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
+bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr &CopyMI) {
SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
@@ -743,7 +743,7 @@ bool InlineSpiller::hoistSpill(LiveInter
TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
MRI.getRegClass(SVI.SpillReg), &TRI);
--MII; // Point to store instruction.
- LIS.InsertMachineInstrInMaps(MII);
+ LIS.InsertMachineInstrInMaps(*MII);
DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
++NumSpills;
@@ -781,7 +781,7 @@ void InlineSpiller::eliminateRedundantSp
MachineInstr *MI = &*(UI++);
if (!MI->isCopy() && !MI->mayStore())
continue;
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
if (LI->getVNInfoAt(Idx) != VNI)
continue;
@@ -860,7 +860,7 @@ bool InlineSpiller::reMaterializeFor(Liv
if (!RI.Reads)
return false;
- SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
+ SlotIndex UseIdx = LIS.getInstructionIndex(*MI).getRegSlot(true);
VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
if (!ParentVNI) {
@@ -1019,7 +1019,7 @@ bool InlineSpiller::coalesceStackAccess(
return false;
DEBUG(dbgs() << "Coalescing stack access: " << *MI);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
if (IsLoad) {
@@ -1051,7 +1051,7 @@ static void dumpMachineInstrRangeWithSlo
dbgs() << '\t' << header << ": " << NextLine;
for (MachineBasicBlock::iterator I = B; I != E; ++I) {
- SlotIndex Idx = LIS.getInstructionIndex(I).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
// If a register was passed in and this instruction has it as a
// destination that is marked as an early clobber, print the
@@ -1138,18 +1138,18 @@ foldMemoryOperand(ArrayRef<std::pair<Mac
continue;
// FoldMI does not define this physreg. Remove the LI segment.
assert(MO->isDead() && "Cannot fold physreg def");
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
LIS.removePhysRegDefAt(Reg, Idx);
}
- LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
+ LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
MI->eraseFromParent();
// Insert any new instructions other than FoldMI into the LIS maps.
assert(!MIS.empty() && "Unexpected empty span of instructions!");
for (MachineInstr &MI : MIS)
if (&MI != FoldMI)
- LIS.InsertMachineInstrInMaps(&MI);
+ LIS.InsertMachineInstrInMaps(MI);
// TII.foldMemoryOperand may have left some implicit operands on the
// instruction. Strip them.
@@ -1252,7 +1252,7 @@ void InlineSpiller::spillAroundUses(unsi
// Find the slot index where this instruction reads and writes OldLI.
// This is usually the def slot, except for tied early clobbers.
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
if (SlotIndex::isSameInstr(Idx, VNI->def))
Idx = VNI->def;
@@ -1268,7 +1268,7 @@ void InlineSpiller::spillAroundUses(unsi
}
if (RI.Writes) {
// Hoist the spill of a sib-reg copy.
- if (hoistSpill(OldLI, MI)) {
+ if (hoistSpill(OldLI, *MI)) {
// This COPY is now dead, the value is already in the stack slot.
MI->getOperand(0).setIsDead();
DeadDefs.push_back(MI);
@@ -1349,11 +1349,11 @@ void InlineSpiller::spillAll() {
for (MachineRegisterInfo::reg_instr_iterator
RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
RI != E; ) {
- MachineInstr *MI = &*(RI++);
- assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
+ MachineInstr &MI = *(RI++);
+ assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
// FIXME: Do this with a LiveRangeEdit callback.
LIS.RemoveMachineInstrFromMaps(MI);
- MI->eraseFromParent();
+ MI.eraseFromParent();
}
}
Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Sat Feb 27 00:40:41 2016
@@ -520,9 +520,10 @@ bool LDVImpl::collectDebugValues(Machine
continue;
}
// DBG_VALUE has no slot index, use the previous instruction instead.
- SlotIndex Idx = MBBI == MBB->begin() ?
- LIS->getMBBStartIdx(MBB) :
- LIS->getInstructionIndex(std::prev(MBBI)).getRegSlot();
+ SlotIndex Idx =
+ MBBI == MBB->begin()
+ ? LIS->getMBBStartIdx(MBB)
+ : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
// Handle consecutive DBG_VALUE instructions with the same slot index.
do {
if (handleDebugValue(MBBI, Idx)) {
@@ -614,7 +615,7 @@ UserValue::addDefsFromCopies(LiveInterva
// Is LocNo extended to reach this copy? If not, another def may be blocking
// it, or we are looking at a wrong value of LI.
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
if (!I.valid() || I.value() != LocNo)
continue;
Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Sat Feb 27 00:40:41 2016
@@ -1454,9 +1454,9 @@ void ConnectedVNInfoEqClasses::Distribut
// called, but it is not a requirement.
SlotIndex Idx;
if (MI->isDebugValue())
- Idx = LIS.getSlotIndexes()->getIndexBefore(MI);
+ Idx = LIS.getSlotIndexes()->getIndexBefore(*MI);
else
- Idx = LIS.getInstructionIndex(MI);
+ Idx = LIS.getInstructionIndex(*MI);
LiveQueryResult LRQ = LI.Query(Idx);
const VNInfo *VNI = MO.readsReg() ? LRQ.valueIn() : LRQ.valueDefined();
// In the case of an <undef> use that isn't tied to any def, VNI will be
@@ -1563,7 +1563,7 @@ bool ConnectedSubRegClasses::findCompone
const LiveInterval::SubRange &SR = *SRInfo.SR;
if ((SR.LaneMask & LaneMask) == 0)
continue;
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
: Pos.getBaseIndex();
const VNInfo *VNI = SR.getVNInfoAt(Pos);
@@ -1598,7 +1598,7 @@ void ConnectedSubRegClasses::rewriteOper
MachineInstr &MI = *MO.getParent();
- SlotIndex Pos = LIS.getInstructionIndex(&MI);
+ SlotIndex Pos = LIS.getInstructionIndex(MI);
unsigned SubRegIdx = MO.getSubReg();
LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
@@ -1672,12 +1672,12 @@ void ConnectedSubRegClasses::computeMain
// in and out of the instruction anymore. We need to add new dead and kill
// flags in these cases.
if (!MO.isUndef()) {
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
if (!LI->liveAt(Pos.getBaseIndex()))
MO.setIsUndef();
}
if (!MO.isDead()) {
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
if (!LI->liveAt(Pos.getDeadSlot()))
MO.setIsDead();
}
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sat Feb 27 00:40:41 2016
@@ -236,7 +236,7 @@ void LiveIntervals::computeRegMasks() {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isRegMask())
continue;
- RegMaskSlots.push_back(Indexes->getInstructionIndex(&MI).getRegSlot());
+ RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
RegMaskBits.push_back(MO.getRegMask());
}
}
@@ -247,7 +247,7 @@ void LiveIntervals::computeRegMasks() {
if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
assert(!MBB.empty() && "empty return block?");
RegMaskSlots.push_back(
- Indexes->getInstructionIndex(&MBB.back()).getRegSlot());
+ Indexes->getInstructionIndex(MBB.back()).getRegSlot());
RegMaskBits.push_back(Mask);
}
@@ -443,7 +443,7 @@ bool LiveIntervals::shrinkToUses(LiveInt
MachineInstr *UseMI = &*(I++);
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
continue;
- SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
+ SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
LiveQueryResult LRQ = li->Query(Idx);
VNInfo *VNI = LRQ.valueIn();
if (!VNI) {
@@ -551,7 +551,7 @@ void LiveIntervals::shrinkToUses(LiveInt
continue;
}
// We only need to visit each instruction once.
- SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
+ SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
if (Idx == LastIdx)
continue;
LastIdx = Idx;
@@ -851,14 +851,13 @@ LiveIntervals::getSpillWeight(bool isDef
}
LiveRange::Segment
-LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
+LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) {
LiveInterval& Interval = createEmptyInterval(reg);
- VNInfo* VN = Interval.getNextValue(
- SlotIndex(getInstructionIndex(startInst).getRegSlot()),
- getVNInfoAllocator());
- LiveRange::Segment S(
- SlotIndex(getInstructionIndex(startInst).getRegSlot()),
- getMBBEndIdx(startInst->getParent()), VN);
+ VNInfo *VN = Interval.getNextValue(
+ SlotIndex(getInstructionIndex(startInst).getRegSlot()),
+ getVNInfoAllocator());
+ LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
+ getMBBEndIdx(startInst.getParent()), VN);
Interval.addSegment(S);
return S;
@@ -1348,7 +1347,7 @@ private:
&& (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
continue;
- const MachineInstr *MI = MO.getParent();
+ const MachineInstr &MI = *MO.getParent();
SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot.getRegSlot();
@@ -1374,7 +1373,7 @@ private:
while (MII != Begin) {
if ((--MII)->isDebugValue())
continue;
- SlotIndex Idx = Indexes->getInstructionIndex(MII);
+ SlotIndex Idx = Indexes->getInstructionIndex(*MII);
// Stop searching when Before is reached.
if (!SlotIndex::isEarlierInstr(Before, Idx))
@@ -1394,9 +1393,9 @@ private:
void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
- SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
- Indexes->removeMachineInstrFromMaps(MI);
- SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
+ SlotIndex OldIndex = Indexes->getInstructionIndex(*MI);
+ Indexes->removeMachineInstrFromMaps(*MI);
+ SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(*MI);
assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
OldIndex < getMBBEndIdx(MI->getParent()) &&
"Cannot handle moves across basic block boundaries.");
@@ -1408,8 +1407,8 @@ void LiveIntervals::handleMove(MachineIn
void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
MachineInstr* BundleStart,
bool UpdateFlags) {
- SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
- SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
+ SlotIndex OldIndex = Indexes->getInstructionIndex(*MI);
+ SlotIndex NewIndex = Indexes->getInstructionIndex(*BundleStart);
HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
HME.updateAllRanges(MI);
}
@@ -1432,7 +1431,7 @@ void LiveIntervals::repairOldRegInRange(
if (MI->isDebugValue())
continue;
- SlotIndex instrIdx = getInstructionIndex(MI);
+ SlotIndex instrIdx = getInstructionIndex(*MI);
bool isStartValid = getInstructionFromIndex(LII->start);
bool isEndValid = getInstructionFromIndex(LII->end);
@@ -1509,18 +1508,18 @@ LiveIntervals::repairIntervalsInRange(Ma
ArrayRef<unsigned> OrigRegs) {
// Find anchor points, which are at the beginning/end of blocks or at
// instructions that already have indexes.
- while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
+ while (Begin != MBB->begin() && !Indexes->hasIndex(*Begin))
--Begin;
- while (End != MBB->end() && !Indexes->hasIndex(End))
+ while (End != MBB->end() && !Indexes->hasIndex(*End))
++End;
SlotIndex endIdx;
if (End == MBB->end())
endIdx = getMBBEndIdx(MBB).getPrevSlot();
else
- endIdx = getInstructionIndex(End);
+ endIdx = getInstructionIndex(*End);
- Indexes->repairIndexesInRange(MBB, Begin, End);
+ Indexes->repairIndexesInRange(MBB, *Begin, *End);
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Sat Feb 27 00:40:41 2016
@@ -42,12 +42,12 @@ void LiveRangeCalc::reset(const MachineF
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
LiveRange &LR, const MachineOperand &MO) {
- const MachineInstr *MI = MO.getParent();
- SlotIndex DefIdx =
- Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
+ const MachineInstr &MI = *MO.getParent();
+ SlotIndex DefIdx =
+ Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
- // Create the def in LR. This may find an existing def.
- LR.createDeadDef(DefIdx, Alloc);
+ // Create the def in LR. This may find an existing def.
+ LR.createDeadDef(DefIdx, Alloc);
}
void LiveRangeCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
@@ -184,7 +184,7 @@ void LiveRangeCalc::extendToUses(LiveRan
// had an early-clobber flag.
isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
}
- UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber);
+ UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
}
// MI is reading Reg. We may have visited MI before if it happens to be
Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Sat Feb 27 00:40:41 2016
@@ -125,7 +125,7 @@ bool LiveRangeEdit::canRematerializeAt(R
// No defining instruction provided.
SlotIndex DefIdx;
if (RM.OrigMI)
- DefIdx = LIS.getInstructionIndex(RM.OrigMI);
+ DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
else {
DefIdx = RM.ParentVNI->def;
RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
@@ -152,8 +152,9 @@ SlotIndex LiveRangeEdit::rematerializeAt
assert(RM.OrigMI && "Invalid remat");
TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
Rematted.insert(RM.ParentVNI);
- return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
- .getRegSlot();
+ return LIS.getSlotIndexes()
+ ->insertMachineInstrInMaps(*--MI, Late)
+ .getRegSlot();
}
void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
@@ -188,9 +189,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInter
// Since we're moving the DefMI load, make sure we're not extending any live
// ranges.
- if (!allUsesAvailableAt(DefMI,
- LIS.getInstructionIndex(DefMI),
- LIS.getInstructionIndex(UseMI)))
+ if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
+ LIS.getInstructionIndex(*UseMI)))
return false;
// We also need to make sure it is safe to move the load.
@@ -210,7 +210,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInter
if (!FoldMI)
return false;
DEBUG(dbgs() << " folded: " << *FoldMI);
- LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
+ LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
UseMI->eraseFromParent();
DefMI->addRegisterDead(LI->reg, nullptr);
Dead.push_back(DefMI);
@@ -220,7 +220,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInter
bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
const MachineOperand &MO) const {
- const MachineInstr *MI = MO.getParent();
+ const MachineInstr &MI = *MO.getParent();
SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
if (LI.Query(Idx).isKill())
return true;
@@ -237,7 +237,7 @@ bool LiveRangeEdit::useIsKill(const Live
/// Find all live intervals that need to shrink, then remove the instruction.
void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
assert(MI->allDefsAreDead() && "Def isn't really dead");
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
// Never delete a bundled instruction.
if (MI->isBundled()) {
@@ -316,7 +316,7 @@ void LiveRangeEdit::eliminateDeadDef(Mac
} else {
if (TheDelegate)
TheDelegate->LRE_WillEraseInstruction(MI);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
++NumDCEDeleted;
}
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Sat Feb 27 00:40:41 2016
@@ -302,16 +302,16 @@ void MachineBasicBlock::print(raw_ostrea
OS << '\n';
}
- for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
+ for (auto &I : instrs()) {
if (Indexes) {
- if (Indexes->hasIndex(&*I))
- OS << Indexes->getInstructionIndex(&*I);
+ if (Indexes->hasIndex(I))
+ OS << Indexes->getInstructionIndex(I);
OS << '\t';
}
OS << '\t';
- if (I->isInsideBundle())
+ if (I.isInsideBundle())
OS << " * ";
- I->print(OS, MST);
+ I.print(OS, MST);
}
// Print the successors of this block according to the CFG.
@@ -826,7 +826,7 @@ MachineBasicBlock::SplitCriticalEdge(Mac
E = Terminators.end(); I != E; ++I) {
if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
NewTerminators.end())
- Indexes->removeMachineInstrFromMaps(*I);
+ Indexes->removeMachineInstrFromMaps(**I);
}
}
@@ -837,13 +837,12 @@ MachineBasicBlock::SplitCriticalEdge(Mac
TII->InsertBranch(*NMBB, Succ, nullptr, Cond, DL);
if (Indexes) {
- for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
- I != E; ++I) {
+ for (MachineInstr &MI : NMBB->instrs()) {
// Some instructions may have been moved to NMBB by updateTerminator(),
// so we first remove any instruction that already has an index.
- if (Indexes->hasIndex(&*I))
- Indexes->removeMachineInstrFromMaps(&*I);
- Indexes->insertMachineInstrInMaps(&*I);
+ if (Indexes->hasIndex(MI))
+ Indexes->removeMachineInstrFromMaps(MI);
+ Indexes->insertMachineInstrInMaps(MI);
}
}
}
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Sat Feb 27 00:40:41 2016
@@ -1039,7 +1039,7 @@ void ScheduleDAGMILive::updatePressureDi
if (I == BB->end())
VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
else {
- LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
+ LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*I));
VNI = LRQ.valueIn();
}
// RegisterPressureTracker guarantees that readsReg is true for LiveUses.
@@ -1050,8 +1050,8 @@ void ScheduleDAGMILive::updatePressureDi
// If this use comes before the reaching def, it cannot be a last use,
// so decrease its pressure change.
if (!SU->isScheduled && SU != &ExitSU) {
- LiveQueryResult LRQ
- = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
+ LiveQueryResult LRQ =
+ LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
PDiff.addPressureChange(Reg, true, &MRI);
@@ -1243,8 +1243,7 @@ unsigned ScheduleDAGMILive::computeCycli
continue;
// Only consider uses of the phi.
- LiveQueryResult LRQ =
- LI.Query(LIS->getInstructionIndex(SU->getInstr()));
+ LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
if (!LRQ.valueIn()->isPHIDef())
continue;
@@ -1293,7 +1292,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else {
// Adjust for missing dead-def flags.
@@ -1329,7 +1328,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else {
// Adjust for missing dead-def flags.
@@ -1705,9 +1704,9 @@ void CopyConstrain::apply(ScheduleDAGMI
MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
if (FirstPos == DAG->end())
return;
- RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
+ RegionBeginIdx = DAG->getLIS()->getInstructionIndex(*FirstPos);
RegionEndIdx = DAG->getLIS()->getInstructionIndex(
- &*priorNonDebug(DAG->end(), DAG->begin()));
+ *priorNonDebug(DAG->end(), DAG->begin()));
for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
SUnit *SU = &DAG->SUnits[Idx];
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Sat Feb 27 00:40:41 2016
@@ -435,8 +435,8 @@ void MachineVerifier::report(const char
assert(MI);
report(msg, MI->getParent());
errs() << "- instruction: ";
- if (Indexes && Indexes->hasIndex(MI))
- errs() << Indexes->getInstructionIndex(MI) << '\t';
+ if (Indexes && Indexes->hasIndex(*MI))
+ errs() << Indexes->getInstructionIndex(*MI) << '\t';
MI->print(errs(), /*SkipOpers=*/true);
errs() << '\n';
}
@@ -760,8 +760,8 @@ MachineVerifier::visitMachineBasicBlockB
// This function gets called for all bundle headers, including normal
// stand-alone unbundled instructions.
void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
- if (Indexes && Indexes->hasIndex(MI)) {
- SlotIndex idx = Indexes->getInstructionIndex(MI);
+ if (Indexes && Indexes->hasIndex(*MI)) {
+ SlotIndex idx = Indexes->getInstructionIndex(*MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
errs() << "Last instruction was at " << lastIndex << '\n';
@@ -849,7 +849,7 @@ void MachineVerifier::visitMachineInstrB
// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
- bool mapped = !LiveInts->isNotInMIMap(MI);
+ bool mapped = !LiveInts->isNotInMIMap(*MI);
if (MI->isDebugValue()) {
if (mapped)
report("Debug instruction has a slot index", MI);
@@ -1023,10 +1023,10 @@ MachineVerifier::visitMachineOperand(con
case MachineOperand::MO_FrameIndex:
if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
- LiveInts && !LiveInts->isNotInMIMap(MI)) {
+ LiveInts && !LiveInts->isNotInMIMap(*MI)) {
int FI = MO->getIndex();
LiveInterval &LI = LiveStks->getInterval(FI);
- SlotIndex Idx = LiveInts->getInstructionIndex(MI);
+ SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
bool stores = MI->mayStore();
bool loads = MI->mayLoad();
@@ -1164,8 +1164,8 @@ void MachineVerifier::checkLiveness(cons
}
// Check LiveInts liveness and kill.
- if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
- SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
+ if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
+ SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
// Check the cached regunit intervals.
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
@@ -1272,8 +1272,8 @@ void MachineVerifier::checkLiveness(cons
report("Multiple virtual register defs in SSA form", MO, MONum);
// Check LiveInts for a live segment, but only for virtual registers.
- if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
- SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
+ if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
+ SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Sat Feb 27 00:40:41 2016
@@ -159,17 +159,16 @@ bool PHIElimination::runOnMachineFunctio
unsigned DefReg = DefMI->getOperand(0).getReg();
if (MRI->use_nodbg_empty(DefReg)) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(DefMI);
+ LIS->RemoveMachineInstrFromMaps(*DefMI);
DefMI->eraseFromParent();
}
}
// Clean up the lowered PHI instructions.
- for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
- I != E; ++I) {
+ for (auto &I : LoweredPHIs) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(I->first);
- MF.DeleteMachineInstr(I->first);
+ LIS->RemoveMachineInstrFromMaps(*I.first);
+ MF.DeleteMachineInstr(I.first);
}
LoweredPHIs.clear();
@@ -310,7 +309,7 @@ void PHIElimination::LowerPHINode(Machin
// Update LiveIntervals for the new copy or implicit def.
if (LIS) {
MachineInstr *NewInstr = std::prev(AfterPHIsIt);
- SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
+ SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*NewInstr);
SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
if (IncomingReg) {
@@ -462,8 +461,8 @@ void PHIElimination::LowerPHINode(Machin
if (LIS) {
if (NewSrcInstr) {
- LIS->InsertMachineInstrInMaps(NewSrcInstr);
- LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
+ LIS->InsertMachineInstrInMaps(*NewSrcInstr);
+ LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
}
if (!SrcUndef &&
@@ -513,7 +512,7 @@ void PHIElimination::LowerPHINode(Machin
assert(KillInst->readsRegister(SrcReg) &&
"Cannot find kill instruction");
- SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
+ SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
SrcLI.removeSegment(LastUseIndex.getRegSlot(),
LIS->getMBBEndIdx(&opBlock));
}
@@ -524,7 +523,7 @@ void PHIElimination::LowerPHINode(Machin
// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
if (reusedIncoming || !IncomingReg) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(MPhi);
+ LIS->RemoveMachineInstrFromMaps(*MPhi);
MF.DeleteMachineInstr(MPhi);
}
}
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Sat Feb 27 00:40:41 2016
@@ -467,7 +467,7 @@ bool RegisterCoalescer::adjustCopiesBack
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
LiveInterval &IntB =
LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
// We have a non-trivially-coalescable copy with IntA being the source and
// IntB being the dest, thus this defines a value number in IntB. If the
@@ -642,7 +642,7 @@ bool RegisterCoalescer::removeCopyByComm
// BValNo is a value number in B that is defined by a copy from A. 'B1' in
// the example above.
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
assert(BValNo != nullptr && BValNo->def == CopyIdx);
@@ -692,7 +692,7 @@ bool RegisterCoalescer::removeCopyByComm
for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
MachineInstr *UseMI = MO.getParent();
unsigned OpNo = &MO - &UseMI->getOperand(0);
- SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
if (US == IntA.end() || US->valno != AValNo)
continue;
@@ -716,7 +716,7 @@ bool RegisterCoalescer::removeCopyByComm
!MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
return false;
if (NewMI != DefMI) {
- LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
MachineBasicBlock::iterator Pos = DefMI;
MBB->insert(Pos, NewMI);
MBB->erase(DefMI);
@@ -746,7 +746,7 @@ bool RegisterCoalescer::removeCopyByComm
UseMO.setReg(NewReg);
continue;
}
- SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
assert(US != IntA.end() && "Use must be live");
if (US->valno != AValNo)
@@ -784,7 +784,7 @@ bool RegisterCoalescer::removeCopyByComm
}
ErasedInstrs.insert(UseMI);
- LIS->RemoveMachineInstrFromMaps(UseMI);
+ LIS->RemoveMachineInstrFromMaps(*UseMI);
UseMI->eraseFromParent();
}
@@ -879,7 +879,7 @@ bool RegisterCoalescer::reMaterializeTri
return false;
LiveInterval &SrcInt = LIS->getInterval(SrcReg);
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
assert(ValNo && "CopyMI input register not live");
if (ValNo->isPHIDef() || ValNo->isUnused())
@@ -969,7 +969,7 @@ bool RegisterCoalescer::reMaterializeTri
}
}
- LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*CopyMI, *NewMI);
CopyMI->eraseFromParent();
ErasedInstrs.insert(CopyMI);
@@ -1017,7 +1017,7 @@ bool RegisterCoalescer::reMaterializeTri
// subranges missing the definition.
LiveInterval &DstInt = LIS->getInterval(DstReg);
if (NewIdx == 0 && DstInt.hasSubRanges()) {
- SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI);
SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber());
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
@@ -1057,7 +1057,7 @@ bool RegisterCoalescer::reMaterializeTri
// vreg1 will see the inteferences with CL but not with CH since
// no live-ranges would have been created for ECX.
// Fix that!
- SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
for (MCRegUnitIterator Units(NewMI->getOperand(0).getReg(), TRI);
Units.isValid(); ++Units)
if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
@@ -1081,7 +1081,7 @@ bool RegisterCoalescer::reMaterializeTri
}
}
- SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
unsigned Reg = NewMIImplDefs[i];
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
@@ -1125,7 +1125,7 @@ bool RegisterCoalescer::eliminateUndefCo
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
- SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
+ SlotIndex Idx = LIS->getInstructionIndex(*CopyMI);
const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
// CopyMI is undef iff SrcReg is not live before the instruction.
if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
@@ -1168,7 +1168,7 @@ bool RegisterCoalescer::eliminateUndefCo
if (MO.isDef() /*|| MO.isUndef()*/)
continue;
const MachineInstr &MI = *MO.getParent();
- SlotIndex UseIdx = LIS->getInstructionIndex(&MI);
+ SlotIndex UseIdx = LIS->getInstructionIndex(MI);
LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
bool isLive;
if (UseMask != ~0u && DstLI.hasSubRanges()) {
@@ -1218,7 +1218,7 @@ void RegisterCoalescer::updateRegDefsUse
// If SrcReg wasn't read, it may still be the case that DstReg is live-in
// because SrcReg is a sub-register.
if (DstInt && !Reads && SubIdx)
- Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
+ Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
// Replace SrcReg with DstReg in all UseMI operands.
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
@@ -1241,8 +1241,8 @@ void RegisterCoalescer::updateRegDefsUse
LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubIdx);
bool IsUndef = true;
SlotIndex MIIdx = UseMI->isDebugValue()
- ? LIS->getSlotIndexes()->getIndexBefore(UseMI)
- : LIS->getInstructionIndex(UseMI);
+ ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
+ : LIS->getInstructionIndex(*UseMI);
SlotIndex UseIdx = MIIdx.getRegSlot(true);
for (LiveInterval::SubRange &S : DstInt->subranges()) {
if ((S.LaneMask & Mask) == 0)
@@ -1273,7 +1273,7 @@ void RegisterCoalescer::updateRegDefsUse
DEBUG({
dbgs() << "\t\tupdated: ";
if (!UseMI->isDebugValue())
- dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
+ dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
dbgs() << *UseMI;
});
}
@@ -1299,7 +1299,7 @@ bool RegisterCoalescer::canJoinPhys(cons
bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
Again = false;
- DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
+ DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
CoalescerPair CP(*TRI);
if (!CP.setRegisters(CopyMI)) {
@@ -1335,7 +1335,7 @@ bool RegisterCoalescer::joinCopy(Machine
// Eliminate undefs.
if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
return false; // Not coalescable.
}
@@ -1346,7 +1346,7 @@ bool RegisterCoalescer::joinCopy(Machine
if (CP.getSrcReg() == CP.getDstReg()) {
LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
- const SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
+ const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
LiveQueryResult LRQ = LI.Query(CopyIdx);
if (VNInfo *DefVNI = LRQ.valueDefined()) {
VNInfo *ReadVNI = LRQ.valueIn();
@@ -1364,7 +1364,7 @@ bool RegisterCoalescer::joinCopy(Machine
}
DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
}
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
return true;
}
@@ -1425,7 +1425,7 @@ bool RegisterCoalescer::joinCopy(Machine
if (!CP.isPartial() && !CP.isPhys()) {
if (adjustCopiesBackFrom(CP, CopyMI) ||
removeCopyByCommutingDef(CP, CopyMI)) {
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
DEBUG(dbgs() << "\tTrivial!\n");
return true;
@@ -1539,8 +1539,8 @@ bool RegisterCoalescer::joinReservedPhys
MachineInstr *DestMI = MRI->getVRegDef(RHS.reg);
CopyMI = &*MRI->use_instr_nodbg_begin(RHS.reg);
- const SlotIndex CopyRegIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
- const SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
+ const SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
+ const SlotIndex DestRegIdx = LIS->getInstructionIndex(*DestMI).getRegSlot();
// We checked above that there are no interfering defs of the physical
// register. However, for this case, where we intent to move up the def of
@@ -1576,7 +1576,7 @@ bool RegisterCoalescer::joinReservedPhys
}
}
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
// We don't track kills for reserved registers.
@@ -2489,7 +2489,7 @@ void JoinVals::eraseInstrs(SmallPtrSetIm
}
ErasedInstrs.insert(MI);
DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
- LIS->RemoveMachineInstrFromMaps(MI);
+ LIS->RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
break;
}
Modified: llvm/trunk/lib/CodeGen/RegisterPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterPressure.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp Sat Feb 27 00:40:41 2016
@@ -271,7 +271,7 @@ SlotIndex RegPressureTracker::getCurrSlo
++IdxPos;
if (IdxPos == MBB->end())
return LIS->getMBBEndIdx(MBB);
- return LIS->getInstructionIndex(IdxPos).getRegSlot();
+ return LIS->getInstructionIndex(*IdxPos).getRegSlot();
}
/// Set the boundary for the top of the region and summarize live ins.
@@ -503,7 +503,7 @@ void RegisterOperands::collect(const Mac
void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
const LiveIntervals &LIS) {
- SlotIndex SlotIdx = LIS.getInstructionIndex(&MI);
+ SlotIndex SlotIdx = LIS.getInstructionIndex(MI);
for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
unsigned Reg = RI->RegUnit;
const LiveRange *LR = getLiveRange(LIS, Reg);
@@ -729,7 +729,7 @@ void RegPressureTracker::recede(const Re
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
// Generate liveness for uses.
for (const RegisterMaskPair &Use : RegOpers.Uses) {
@@ -794,7 +794,7 @@ void RegPressureTracker::recedeSkipDebug
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
// Open the top of the region using slot indexes.
if (RequireIntervals && isTopClosed())
@@ -808,7 +808,7 @@ void RegPressureTracker::recede(SmallVec
RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {
- SlotIndex SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
} else if (RequireIntervals) {
RegOpers.detectDeadDefs(MI, *LIS);
@@ -969,7 +969,7 @@ void RegPressureTracker::bumpUpwardPress
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
// Account for register pressure similar to RegPressureTracker::recede().
RegisterOperands RegOpers;
@@ -1154,7 +1154,7 @@ static LaneBitmask findUseBetween(unsign
if (MO.isUndef())
continue;
const MachineInstr *MI = MO.getParent();
- SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
unsigned SubRegIdx = MO.getSubReg();
LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
@@ -1214,7 +1214,7 @@ void RegPressureTracker::bumpDownwardPre
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
// Account for register pressure similar to RegPressureTracker::recede().
RegisterOperands RegOpers;
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Sat Feb 27 00:40:41 2016
@@ -929,7 +929,7 @@ void ScheduleDAGInstrs::buildSchedGraph(
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI);
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
}
if (PDiffs != nullptr)
Modified: llvm/trunk/lib/CodeGen/SlotIndexes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SlotIndexes.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SlotIndexes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SlotIndexes.cpp Sat Feb 27 00:40:41 2016
@@ -150,9 +150,9 @@ void SlotIndexes::repairIndexesInRange(M
// does the same thing.
// Find anchor points, which are at the beginning/end of blocks or at
// instructions that already have indexes.
- while (Begin != MBB->begin() && !hasIndex(Begin))
+ while (Begin != MBB->begin() && !hasIndex(*Begin))
--Begin;
- while (End != MBB->end() && !hasIndex(End))
+ while (End != MBB->end() && !hasIndex(*End))
++End;
bool includeStart = (Begin == MBB->begin());
@@ -160,13 +160,13 @@ void SlotIndexes::repairIndexesInRange(M
if (includeStart)
startIdx = getMBBStartIdx(MBB);
else
- startIdx = getInstructionIndex(Begin);
+ startIdx = getInstructionIndex(*Begin);
SlotIndex endIdx;
if (End == MBB->end())
endIdx = getMBBEndIdx(MBB);
else
- endIdx = getInstructionIndex(End);
+ endIdx = getInstructionIndex(*End);
// FIXME: Conceptually, this code is implementing an iterator on MBB that
// optionally includes an additional position prior to MBB->begin(), indicated
@@ -199,7 +199,7 @@ void SlotIndexes::repairIndexesInRange(M
} else {
--ListI;
if (SlotMI)
- removeMachineInstrFromMaps(SlotMI);
+ removeMachineInstrFromMaps(*SlotMI);
}
}
@@ -209,7 +209,7 @@ void SlotIndexes::repairIndexesInRange(M
--I;
MachineInstr *MI = I;
if (!MI->isDebugValue() && mi2iMap.find(MI) == mi2iMap.end())
- insertMachineInstrInMaps(MI);
+ insertMachineInstrInMaps(*MI);
}
}
Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Sat Feb 27 00:40:41 2016
@@ -68,7 +68,7 @@ SlotIndex SplitAnalysis::computeLastSpli
if (FirstTerm == MBB->end())
LSP.first = MBBEnd;
else
- LSP.first = LIS.getInstructionIndex(FirstTerm);
+ LSP.first = LIS.getInstructionIndex(*FirstTerm);
// If there is a landing pad successor, also find the call instruction.
if (!LPad)
@@ -79,7 +79,7 @@ SlotIndex SplitAnalysis::computeLastSpli
I != E;) {
--I;
if (I->isCall()) {
- LSP.second = LIS.getInstructionIndex(I);
+ LSP.second = LIS.getInstructionIndex(*I);
break;
}
}
@@ -129,7 +129,7 @@ void SplitAnalysis::analyzeUses() {
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
if (!MO.isUndef())
- UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
+ UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
array_pod_sort(UseSlots.begin(), UseSlots.end());
@@ -438,8 +438,9 @@ VNInfo *SplitEditor::defFromParent(unsig
// Can't remat, just insert a copy from parent.
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
.addReg(Edit->getReg());
- Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
- .getRegSlot();
+ Def = LIS.getSlotIndexes()
+ ->insertMachineInstrInMaps(*CopyMI, Late)
+ .getRegSlot();
++NumCopies;
}
@@ -638,7 +639,7 @@ void SplitEditor::removeBackCopies(Small
DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
LIS.removeVRegDefAt(*LI, Def);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
// Adjust RegAssign if a register assignment is killed at Def. We want to
@@ -654,7 +655,7 @@ void SplitEditor::removeBackCopies(Small
DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
} else {
- SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
+ SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot();
DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
AssignI.setStop(Kill);
}
@@ -964,7 +965,7 @@ void SplitEditor::rewriteAssigned(bool E
// <undef> operands don't really read the register, so it doesn't matter
// which register we choose. When the use operand is tied to a def, we must
// use the same register as the def, so just do that always.
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
if (MO.isDef() || MO.isUndef())
Idx = Idx.getRegSlot(MO.isEarlyClobber());
Modified: llvm/trunk/lib/CodeGen/StackColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackColoring.cpp Sat Feb 27 00:40:41 2016
@@ -395,7 +395,7 @@ void StackColoring::calculateLiveInterva
int Slot = Mo.getIndex();
assert(Slot >= 0 && "Invalid slot");
- SlotIndex ThisIndex = Indexes->getInstructionIndex(MI);
+ SlotIndex ThisIndex = Indexes->getInstructionIndex(*MI);
if (IsStart) {
if (!Starts[Slot].isValid() || Starts[Slot] > ThisIndex)
@@ -569,7 +569,7 @@ void StackColoring::remapInstructions(De
// If we *don't* protect the user from escaped allocas, don't bother
// validating the instructions.
if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) {
- SlotIndex Index = Indexes->getInstructionIndex(&I);
+ SlotIndex Index = Indexes->getInstructionIndex(I);
const LiveInterval *Interval = &*Intervals[FromSlot];
assert(Interval->find(Index) != Interval->end() &&
"Found instruction usage outside of live range.");
@@ -628,7 +628,7 @@ void StackColoring::removeInvalidSlotRan
// Check that the used slot is inside the calculated lifetime range.
// If it is not, warn about it and invalidate the range.
LiveInterval *Interval = &*Intervals[Slot];
- SlotIndex Index = Indexes->getInstructionIndex(&I);
+ SlotIndex Index = Indexes->getInstructionIndex(I);
if (Interval->find(Index) == Interval->end()) {
Interval->clear();
DEBUG(dbgs()<<"Invalidating range #"<<Slot<<"\n");
Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Sat Feb 27 00:40:41 2016
@@ -401,7 +401,7 @@ static bool isCopyToReg(MachineInstr &MI
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
LiveIntervals *LIS) {
if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
- !LIS->isNotInMIMap(MI)) {
+ !LIS->isNotInMIMap(*MI)) {
// FIXME: Sometimes tryInstructionTransform() will add instructions and
// test whether they can be folded before keeping them. In this case it
// sets a kill before recursively calling tryInstructionTransform() again.
@@ -414,7 +414,7 @@ static bool isPlainlyKilled(MachineInstr
if (!LI.hasAtLeastOneValue())
return false;
- SlotIndex useIdx = LIS->getInstructionIndex(MI);
+ SlotIndex useIdx = LIS->getInstructionIndex(*MI);
LiveInterval::const_iterator I = LI.find(useIdx);
assert(I != LI.end() && "Reg must be live-in to use.");
return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
@@ -706,7 +706,7 @@ TwoAddressInstructionPass::convertInstTo
bool Sunk = false;
if (LIS)
- LIS->ReplaceMachineInstrInMaps(mi, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
if (NewMI->findRegisterUseOperand(RegB, false, TRI))
// FIXME: Temporary workaround. If the new instruction doesn't
@@ -1521,13 +1521,13 @@ TwoAddressInstructionPass::processTiedPa
DistanceMap[MI] = ++Dist;
if (LIS) {
- LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
+ LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
if (TargetRegisterInfo::isVirtualRegister(RegA)) {
LiveInterval &LI = LIS->getInterval(RegA);
VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
SlotIndex endIdx =
- LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
+ LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
}
}
@@ -1582,7 +1582,7 @@ TwoAddressInstructionPass::processTiedPa
// Update LiveIntervals.
if (LIS) {
LiveInterval &LI = LIS->getInterval(RegB);
- SlotIndex MIIdx = LIS->getInstructionIndex(MI);
+ SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
LiveInterval::const_iterator I = LI.find(MIIdx);
assert(I != LI.end() && "RegB must be live-in to use.");
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Sat Feb 27 00:40:41 2016
@@ -329,7 +329,7 @@ bool VirtRegRewriter::readsUndefSubreg(c
unsigned Reg = MO.getReg();
const LiveInterval &LI = LIS->getInterval(Reg);
const MachineInstr &MI = *MO.getParent();
- SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
+ SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
// This code is only meant to handle reading undefined subregisters which
// we couldn't properly detect before.
assert(LI.liveAt(BaseIndex) &&
@@ -438,7 +438,7 @@ void VirtRegRewriter::rewrite() {
++NumIdCopies;
DEBUG(dbgs() << "Deleting identity copy.\n");
if (Indexes)
- Indexes->removeMachineInstrFromMaps(MI);
+ Indexes->removeMachineInstrFromMaps(*MI);
// It's safe to erase MI because MII has already been incremented.
MI->eraseFromParent();
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp Sat Feb 27 00:40:41 2016
@@ -320,7 +320,7 @@ void A57ChainingConstraint::addInterChai
static bool regJustKilledBefore(const LiveIntervals &LIs, unsigned reg,
const MachineInstr &MI) {
const LiveInterval &LI = LIs.getInterval(reg);
- SlotIndex SI = LIs.getInstructionIndex(&MI);
+ SlotIndex SI = LIs.getInstructionIndex(MI);
return LI.expiredAt(SI);
}
Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Sat Feb 27 00:40:41 2016
@@ -268,19 +268,19 @@ MachineBasicBlock::iterator SILoadStore
.addOperand(*Dest1)
.addReg(DestReg, RegState::Kill, SubRegIdx1);
- LIS->InsertMachineInstrInMaps(Read2);
+ LIS->InsertMachineInstrInMaps(*Read2);
// repairLiveintervalsInRange() doesn't handle physical register, so we have
// to update the M0 range manually.
- SlotIndex PairedIndex = LIS->getInstructionIndex(Paired);
+ SlotIndex PairedIndex = LIS->getInstructionIndex(*Paired);
LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI));
LiveRange::Segment *M0Segment = M0Range.getSegmentContaining(PairedIndex);
bool UpdateM0Range = M0Segment->end == PairedIndex.getRegSlot();
// The new write to the original destination register is now the copy. Steal
// the old SlotIndex.
- LIS->ReplaceMachineInstrInMaps(I, Copy0);
- LIS->ReplaceMachineInstrInMaps(Paired, Copy1);
+ LIS->ReplaceMachineInstrInMaps(*I, *Copy0);
+ LIS->ReplaceMachineInstrInMaps(*Paired, *Copy1);
I->eraseFromParent();
Paired->eraseFromParent();
@@ -291,7 +291,7 @@ MachineBasicBlock::iterator SILoadStore
LIS->createAndComputeVirtRegInterval(DestReg);
if (UpdateM0Range) {
- SlotIndex Read2Index = LIS->getInstructionIndex(Read2);
+ SlotIndex Read2Index = LIS->getInstructionIndex(*Read2);
M0Segment->end = Read2Index.getRegSlot();
}
@@ -340,7 +340,7 @@ MachineBasicBlock::iterator SILoadStoreO
// repairLiveintervalsInRange() doesn't handle physical register, so we have
// to update the M0 range manually.
- SlotIndex PairedIndex = LIS->getInstructionIndex(Paired);
+ SlotIndex PairedIndex = LIS->getInstructionIndex(*Paired);
LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI));
LiveRange::Segment *M0Segment = M0Range.getSegmentContaining(PairedIndex);
bool UpdateM0Range = M0Segment->end == PairedIndex.getRegSlot();
@@ -359,8 +359,8 @@ MachineBasicBlock::iterator SILoadStoreO
// XXX - How do we express subregisters here?
unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg() };
- LIS->RemoveMachineInstrFromMaps(I);
- LIS->RemoveMachineInstrFromMaps(Paired);
+ LIS->RemoveMachineInstrFromMaps(*I);
+ LIS->RemoveMachineInstrFromMaps(*Paired);
I->eraseFromParent();
Paired->eraseFromParent();
@@ -368,7 +368,7 @@ MachineBasicBlock::iterator SILoadStoreO
LIS->repairIntervalsInRange(MBB, Write2, Write2, OrigRegs);
if (UpdateM0Range) {
- SlotIndex Write2Index = LIS->getInstructionIndex(Write2);
+ SlotIndex Write2Index = LIS->getInstructionIndex(*Write2);
M0Segment->end = Write2Index.getRegSlot();
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp Sat Feb 27 00:40:41 2016
@@ -295,7 +295,7 @@ static bool isDefBetween(unsigned Reg,
const MachineInstr* MI = &*UI;
if (MI->isDebugValue())
continue;
- SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
if (InstSlot >= First && InstSlot <= Last)
return true;
}
@@ -357,9 +357,9 @@ void SIScheduleBlock::initRegPressure(Ma
for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
unsigned Reg = RegMaskPair.RegUnit;
if (TargetRegisterInfo::isVirtualRegister(Reg) &&
- isDefBetween(Reg, LIS->getInstructionIndex(BeginBlock).getRegSlot(),
- LIS->getInstructionIndex(EndBlock).getRegSlot(),
- MRI, LIS)) {
+ isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(),
+ LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI,
+ LIS)) {
LiveOutRegs.insert(Reg);
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Sat Feb 27 00:40:41 2016
@@ -340,7 +340,7 @@ void HexagonExpandCondsets::shrinkToUses
}
// Extend the live segment to the beginning of the next one.
LiveInterval::iterator End = LI.end();
- SlotIndex S = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex S = LIS->getInstructionIndex(*MI).getRegSlot();
LiveInterval::iterator T = LI.FindSegmentContaining(S);
assert(T != End);
LiveInterval::iterator N = std::next(T);
@@ -416,8 +416,8 @@ void HexagonExpandCondsets::terminateSeg
/// function is used to update the live intervals while these transformations
/// are being done.
void HexagonExpandCondsets::addInstrToLiveness(MachineInstr *MI) {
- SlotIndex MX = LIS->isNotInMIMap(MI) ? LIS->InsertMachineInstrInMaps(MI)
- : LIS->getInstructionIndex(MI);
+ SlotIndex MX = LIS->isNotInMIMap(*MI) ? LIS->InsertMachineInstrInMaps(*MI)
+ : LIS->getInstructionIndex(*MI);
DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI);
MX = MX.getRegSlot();
@@ -543,7 +543,7 @@ void HexagonExpandCondsets::addInstrToLi
/// instruction from the program. As with "addInstrToLiveness", this function
/// is called while the program code is being changed.
void HexagonExpandCondsets::removeInstrFromLiveness(MachineInstr *MI) {
- SlotIndex MX = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex MX = LIS->getInstructionIndex(*MI).getRegSlot();
DEBUG(dbgs() << "removing instr\n " << MX << " " << *MI);
// For each def in MI:
@@ -635,7 +635,7 @@ void HexagonExpandCondsets::removeInstrF
continue;
Uses.push_back(R);
}
- LIS->RemoveMachineInstrFromMaps(MI);
+ LIS->RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
for (unsigned i = 0, n = Uses.size(); i < n; ++i) {
LiveInterval &LI = LIS->getInterval(Uses[i]);
Modified: llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp?rev=262115&r1=262114&r2=262115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp Sat Feb 27 00:40:41 2016
@@ -99,7 +99,7 @@ protected:
// %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
// and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
- SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
+ SlotIndex FMAIdx = LIS->getInstructionIndex(*MI);
VNInfo *AddendValNo =
LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
@@ -325,7 +325,7 @@ protected:
// Remove the (now unused) copy.
DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
- LIS->RemoveMachineInstrFromMaps(AddendMI);
+ LIS->RemoveMachineInstrFromMaps(*AddendMI);
AddendMI->eraseFromParent();
Changed = true;
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