[PATCH] D17141: [ARM] Adding IEEE-754 SIMD detection to loop vectorizer

[Owen Anderson via llvm-commits]

resistor added inline comments.

================
Comment at: include/llvm/Analysis/TargetTransformInfo.h:373
@@ +372,3 @@
+  /// and SLP vectorization without -ffast-math option.
+  bool isSIMDIEEE754() const;
+
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hfinkel wrote:
> What does one thing have to do with the other (i.e. what does IEEE floating point have to do with allowing fast-math)? The underlying issue is that, without fast-math, the numeric representation, and the operations on numbers in that representation, should be the same. fast-math allows the use of alternate representations and operations (so long as they're not too different), but also allows reassociation. To allow vectorizing reductions, we need reassociation as well (which is a separate matter from the potential change in operational semantics).
To pile on a bit, it's not just about SIMD.  Darwin uses NEON for scalar floating point as well, rather than VFP.


http://reviews.llvm.org/D17141