[PATCH] D17541: X86: Load and ZeroExtend i1 value

[Elena Demikhovsky via llvm-commits]

delena created this revision.
delena added reviewers: DavidKreitzer, qcolombet, RKSimon.
delena added subscribers: llvm-commits, igorb.
delena set the repository for this revision to rL LLVM.

Optimized loading (zextload) of i1 value from memory.
This patch is a partial revert of  https://llvm.org/svn/llvm-project/llvm/trunk@237793.
Extra "and" causes performance degradation.

We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits.
I described this assumption in the documentation. 


Repository:
  rL LLVM

http://reviews.llvm.org/D17541

Files:
  ../docs/LangRef.rst
  ../lib/Target/X86/X86InstrAVX512.td
  ../lib/Target/X86/X86InstrCompiler.td
  ../test/CodeGen/X86/and-encoding.ll
  ../test/CodeGen/X86/avx512-insert-extract.ll
  ../test/CodeGen/X86/avx512-mask-op.ll
  ../test/CodeGen/X86/masked_gather_scatter.ll
  ../test/CodeGen/X86/x86-shrink-wrapping.ll

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