[llvm] r261417 - [X86] Add some missing reversed forms of XOP instructions.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Feb 20 00:20:17 2016
New Revision: 261417

URL: http://llvm.org/viewvc/llvm-project?rev=261417&view=rev
Log:
[X86] Add some missing reversed forms of XOP instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrXOP.td
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt

Modified: llvm/trunk/lib/Target/X86/X86InstrXOP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrXOP.td?rev=261417&r1=261416&r2=261417&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrXOP.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrXOP.td Sat Feb 20 00:20:17 2016
@@ -246,6 +246,13 @@ multiclass xop4op<bits<8> opc, string Op
              (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
               VR128:$src3))]>,
            XOP_4V, VEX_I8IMM;
+  // For disassembler
+  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
+  def rr_REV : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
+           (ins VR128:$src1, VR128:$src2, VR128:$src3),
+           !strconcat(OpcodeStr,
+           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+           []>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
 }
 
 let ExeDomain = SSEPackedInt in {
@@ -276,6 +283,13 @@ multiclass xop4op256<bits<8> opc, string
              (Int VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
               VR256:$src3))]>,
            XOP_4V, VEX_I8IMM, VEX_L;
+  // For disassembler
+  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
+  def rrY_REV : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
+           (ins VR256:$src1, VR256:$src2, VR256:$src3),
+           !strconcat(OpcodeStr,
+           "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+           []>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
 }
 
 let ExeDomain = SSEPackedInt in
@@ -312,6 +326,14 @@ multiclass xop5op<bits<8> opc, string Op
         "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
         [(set VR128:$dst,
            (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
+  // For disassembler
+  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
+  def rr_REV : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
+        (ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
+        !strconcat(OpcodeStr,
+        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
+        []>, VEX_W, MemOp4;
+
   def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
         (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
         !strconcat(OpcodeStr,
@@ -332,6 +354,13 @@ multiclass xop5op<bits<8> opc, string Op
         [(set VR256:$dst,
            (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
         VEX_L;
+  // For disassembler
+  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
+  def rrY_REV : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
+        (ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
+        !strconcat(OpcodeStr,
+        "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
+        []>, VEX_W, MemOp4, VEX_L;
 }
 
 let ExeDomain = SSEPackedDouble in

Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=261417&r1=261416&r2=261417&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sat Feb 20 00:20:17 2016
@@ -905,12 +905,21 @@
 # CHECK: vpcmov %ymm1, %ymm2, %ymm3, %ymm4
 0x8f 0xe8 0x64 0xa2 0xe2 0x10
 
+# CHECK: vpcmov %ymm2, %ymm1, %ymm3, %ymm4
+0x8f 0xe8 0xe4 0xa2 0xe2 0x10
+
 # CHECK: vpcmov (%rax), %ymm2, %ymm3, %ymm4
 0x8f 0xe8 0xe4 0xa2 0x20 0x20
 
 # CHECK: vpcmov %ymm1, (%rax), %ymm3, %ymm4
 0x8f 0xe8 0x64 0xa2 0x20 0x10
 
+# CHECK: vpermil2pd $0, %xmm3, %xmm2, %xmm1, %xmm0
+0xc4 0xe3 0x71 0x49 0xc2 0x30
+
+# CHECK: vpermil2pd $0, %xmm2, %xmm3, %xmm1, %xmm0
+0xc4 0xe3 0xf1 0x49 0xc2 0x30
+
 # CHECK: vpcomeqb  %xmm6, %xmm4, %xmm2
 0x8f 0xe8 0x58 0xcc 0xd6 0x04