[PATCH] D17350: [AArch64][ShrinkWrap] Fix bug in prolog clobbering live reg when shrink wrapping.

[Quentin Colombet via llvm-commits]

qcolombet added inline comments.

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Comment at: test/CodeGen/AArch64/arm64-shrink-wrapping.ll:645
@@ +644,3 @@
+; ENABLE-DAG: str w[[DIV2]],
+
+define i32 @stack_realign(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) {
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I know this is painful (I’ve done quite a few time already ;)), but could you add the DISABLE check and regular CHECK to minimize the ENABLE/DISABLE differences.

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Comment at: test/CodeGen/AArch64/arm64-shrink-wrapping.ll:672
@@ +671,3 @@
+; ENABLE: add x29, sp, #{{[0-9]+}}
+; ENABLE: lsl {{w[0-9]+}}, w0, w1
+
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In this case, since both shrink-wrapped and non-shrink-wrapped tests are the same, you should use CHECK lines everywhere.


http://reviews.llvm.org/D17350