[PATCH] D17277: AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsics

[Nicolai Hähnle via llvm-commits]

nhaehnle updated this revision to Diff 48371.
nhaehnle added a comment.

Removed the tfe argument and use more conservative memory access attributes
by overriding mayLoad and hasSideEffects only for buffer_store_format_*.

About the index and offset arguments: index can't be merged since it uses
the stride in the buffer resource. The various offsets could be merged, but
it seems a lot of fighting with TableGen for little benefit.

If anything, I would try to unify the patterns for load and store before that,
but I couldn't figure out how to do that. The natural idea is to have a
multiclass BufferLoadStorePatterns and use !cast<MUBUF>(name#_OFFSET) etc.
to get the instructions. The problem is that load and store have different
numbers of arguments, and I couldn't figure out how to concat the operand
lists of dag nodes.

Unless there are suggestions for this or other strong objections, I'd rather
commit this as is.


http://reviews.llvm.org/D17277

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll

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