[www] r261146 - [EuroLLVM] Add another poster.

Arnaud A. de Grandmaison via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 17 12:13:54 PST 2016


Author: aadg
Date: Wed Feb 17 14:13:54 2016
New Revision: 261146

URL: http://llvm.org/viewvc/llvm-project?rev=261146&view=rev
Log:
[EuroLLVM] Add another poster.

Modified:
    www/trunk/devmtg/2016-03/index.html

Modified: www/trunk/devmtg/2016-03/index.html
URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2016-03/index.html?rev=261146&r1=261145&r2=261146&view=diff
==============================================================================
--- www/trunk/devmtg/2016-03/index.html (original)
+++ www/trunk/devmtg/2016-03/index.html Wed Feb 17 14:13:54 2016
@@ -923,6 +923,38 @@ support them. This includes :
   <li>how to relax call/return when you have multiple return address sizes.</li>
 </ul>
 
+<p>
+<b><a id="poster7">Automatic Identification of Accelerators for Hybrid HW-SW Execution</a></b><br>
+<i>Georgios Zacharopoulos - University of Lugano</i><br>
+<i>Giovanni Ansaloni - University of Lugano</i><br>
+<i>Laura Pozzi - University of Lugano</i><br>
+While the number of transistors that can be put on a chip significantly
+increases, as suggested by Moore's law, the dark silicon problem rises. This is
+due to the power consumption not dropping at a corresponding rate, which
+generates overheating issues. Accelerator-enhanced architectures can provide an
+efficient solution to this and lead us to a hybrid HW-SW execution, where
+computationally intensive parts can be performed by custom hardware. An
+automation of this process is needed, so that applications in high-level
+languages can be mapped to hardware and software directly. The process needs,
+first, an automatic technique for identifying the parts of the computation that
+should be accelerated, and secondly, an automated way of synthesising these
+parts onto hardware. Under the scope of this paper, we are focusing on the
+first part of this process, and we present the automatic identification of the
+most computationally demanding parts, also known as custom instructions. The
+state-of-the-art identification approaches have certain limitations, as custom
+instruction selection is mostly performed within the scope of single Basic
+Blocks. We introduce a novel selection strategy, implemented within the LLVM
+framework, that carries out identification beyond the scope of a single Basic
+Block and identifies Regions within the Control Flow Graph, as subgraphs of it.
+Specific I/O constraints and area occupation metrics are taken into
+consideration, in order to obtain Regions that would provide maximum speedup,
+under architectural constraints, when transferred to hardware. For our final
+experimentation and evaluation phase, kernels from the signal and image
+processing domain are evaluated, and promising initial results show that the
+identification technique proposed is often capable of mimicking manual designer
+decisions.
+</p>
+
 <div class="www_sectiontitle" id="BoFsAbstracts">BoFs abstracts</div>
 <p>
 <b><a id="bof1">LLVM Foundation</a></b><br>




More information about the llvm-commits mailing list