[PATCH] D17284: TableGen: Constrain inputs of reg_sequence to be same type

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.

http://reviews.llvm.org/D17284

Files:
  utils/TableGen/CodeGenDAGPatterns.cpp

Index: utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- utils/TableGen/CodeGenDAGPatterns.cpp
+++ utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1867,6 +1867,9 @@
         return false;
       }
 
+      // TODO: Should verify that the output register size matches N * the input
+      // size.
+
       if (!isOperandClass(getChild(0), "RegisterClass")) {
         TP.error("REG_SEQUENCE requires a RegisterClass for first operand!");
         return false;
@@ -1879,6 +1882,11 @@
                    itostr(I + 1) + "!");
           return false;
         }
+
+        if (I > 1) {
+          assert(getChild(I)->getNumTypes() == 1 && "FIXME: Unhandled");
+          MadeChange |= getChild(I)->UpdateNodeType(0, getChild(1)->getExtType(0), TP);
+        }
       }
     }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D17284.48039.patch
Type: text/x-patch
Size: 832 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160216/870388a1/attachment.bin>