[llvm] r260585 - [WebAssembly] Reformat WebAssemblyFrameLowering and WebAssemblyISelLowering
Derek Schuff via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 11 12:57:09 PST 2016
Author: dschuff
Date: Thu Feb 11 14:57:09 2016
New Revision: 260585
URL: http://llvm.org/viewvc/llvm-project?rev=260585&view=rev
Log:
[WebAssembly] Reformat WebAssemblyFrameLowering and WebAssemblyISelLowering
Reviewers: sunfish, jfb
Subscribers: jfb, dschuff
Differential Revision: http://reviews.llvm.org/D17156
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp?rev=260585&r1=260584&r2=260585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp Thu Feb 11 14:57:09 2016
@@ -99,9 +99,9 @@ void WebAssemblyFrameLowering::emitProlo
// Load the SP value.
BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32),
StackSize ? SPReg : (unsigned)WebAssembly::SP32)
- .addImm(0) // offset
- .addReg(SPReg) // addr
- .addImm(2) // p2align
+ .addImm(0) // offset
+ .addReg(SPReg) // addr
+ .addImm(2) // p2align
.addMemOperand(LoadMMO);
unsigned OffsetReg = 0;
@@ -110,8 +110,7 @@ void WebAssemblyFrameLowering::emitProlo
OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
.addImm(StackSize);
- BuildMI(MBB, InsertPt, DL,
- TII->get(WebAssembly::SUB_I32),
+ BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::SUB_I32),
WebAssembly::SP32)
.addReg(SPReg)
.addReg(OffsetReg);
@@ -126,17 +125,18 @@ void WebAssemblyFrameLowering::emitProlo
}
if (StackSize) {
assert(OffsetReg);
- // The SP32 register now has the new stacktop. Also write it back to memory.
- BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
- .addExternalSymbol(SPSymbol);
- auto *MMO = new MachineMemOperand(MachinePointerInfo(),
- MachineMemOperand::MOStore, 4, 4);
- BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32)
- .addImm(0)
- .addReg(OffsetReg)
- .addImm(2) // p2align
- .addReg(WebAssembly::SP32)
- .addMemOperand(MMO);
+ // The SP32 register now has the new stacktop. Also write it back to memory.
+ BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
+ .addExternalSymbol(SPSymbol);
+ auto *MMO = new MachineMemOperand(MachinePointerInfo(),
+ MachineMemOperand::MOStore, 4, 4);
+ BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32),
+ WebAssembly::SP32)
+ .addImm(0)
+ .addReg(OffsetReg)
+ .addImm(2) // p2align
+ .addReg(WebAssembly::SP32)
+ .addMemOperand(MMO);
}
}
@@ -160,7 +160,8 @@ void WebAssemblyFrameLowering::emitEpilo
if (StackSize) {
BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
.addImm(StackSize);
- BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), WebAssembly::SP32)
+ BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32),
+ WebAssembly::SP32)
.addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32)
.addReg(OffsetReg);
}
@@ -171,10 +172,11 @@ void WebAssemblyFrameLowering::emitEpilo
.addExternalSymbol(SPSymbol);
auto *MMO = new MachineMemOperand(MachinePointerInfo(),
MachineMemOperand::MOStore, 4, 4);
- BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32)
+ BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32),
+ WebAssembly::SP32)
.addImm(0)
.addReg(OffsetReg)
- .addImm(2) // p2align
+ .addImm(2) // p2align
.addReg((!StackSize && hasFP(MF)) ? WebAssembly::FP32 : WebAssembly::SP32)
.addMemOperand(MMO);
}
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.h?rev=260585&r1=260584&r2=260585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.h Thu Feb 11 14:57:09 2016
@@ -21,16 +21,16 @@
namespace llvm {
class WebAssemblyFrameLowering final : public TargetFrameLowering {
-public:
+ public:
WebAssemblyFrameLowering()
: TargetFrameLowering(StackGrowsDown, /*StackAlignment=*/16,
/*LocalAreaOffset=*/0,
/*TransientStackAlignment=*/16,
/*StackRealignable=*/true) {}
- void
- eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const override;
+ void eliminateCallFramePseudoInstr(
+ MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I) const override;
/// These methods insert prolog and epilog code into the function.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
@@ -40,6 +40,6 @@ public:
bool hasReservedCallFrame(const MachineFunction &MF) const override;
};
-} // end namespace llvm
+} // end namespace llvm
#endif
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=260585&r1=260584&r2=260585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Thu Feb 11 14:57:09 2016
@@ -149,8 +149,7 @@ bool WebAssemblyTargetLowering::isOffset
MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
EVT VT) const {
unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
- if (BitWidth > 1 && BitWidth < 8)
- BitWidth = 8;
+ if (BitWidth > 1 && BitWidth < 8) BitWidth = 8;
if (BitWidth > 64) {
BitWidth = 64;
@@ -164,13 +163,13 @@ MVT WebAssemblyTargetLowering::getScalar
return Result;
}
-const char *
-WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
+const char *WebAssemblyTargetLowering::getTargetNodeName(
+ unsigned Opcode) const {
switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
- case WebAssemblyISD::FIRST_NUMBER:
- break;
-#define HANDLE_NODETYPE(NODE) \
- case WebAssemblyISD::NODE: \
+ case WebAssemblyISD::FIRST_NUMBER:
+ break;
+#define HANDLE_NODETYPE(NODE) \
+ case WebAssemblyISD::NODE: \
return "WebAssemblyISD::" #NODE;
#include "WebAssemblyISD.def"
#undef HANDLE_NODETYPE
@@ -185,17 +184,17 @@ WebAssemblyTargetLowering::getRegForInli
// WebAssembly register class.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
- case 'r':
- assert(VT != MVT::iPTR && "Pointer MVT not expected here");
- if (VT.isInteger() && !VT.isVector()) {
- if (VT.getSizeInBits() <= 32)
- return std::make_pair(0U, &WebAssembly::I32RegClass);
- if (VT.getSizeInBits() <= 64)
- return std::make_pair(0U, &WebAssembly::I64RegClass);
- }
- break;
- default:
- break;
+ case 'r':
+ assert(VT != MVT::iPTR && "Pointer MVT not expected here");
+ if (VT.isInteger() && !VT.isVector()) {
+ if (VT.getSizeInBits() <= 32)
+ return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT.getSizeInBits() <= 64)
+ return std::make_pair(0U, &WebAssembly::I64RegClass);
+ }
+ break;
+ default:
+ break;
}
}
@@ -219,28 +218,24 @@ bool WebAssemblyTargetLowering::isLegalA
// WebAssembly offsets are added as unsigned without wrapping. The
// isLegalAddressingMode gives us no way to determine if wrapping could be
// happening, so we approximate this by accepting only non-negative offsets.
- if (AM.BaseOffs < 0)
- return false;
+ if (AM.BaseOffs < 0) return false;
// WebAssembly has no scale register operands.
- if (AM.Scale != 0)
- return false;
+ if (AM.Scale != 0) return false;
// Everything else is legal.
return true;
}
bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
- EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/,
- bool *Fast) const {
+ EVT /*VT*/, unsigned /*AddrSpace*/, unsigned /*Align*/, bool *Fast) const {
// WebAssembly supports unaligned accesses, though it should be declared
// with the p2align attribute on loads and stores which do so, and there
// may be a performance impact. We tell LLVM they're "fast" because
// for the kinds of things that LLVM uses this for (merging adjacent stores
// of constants, etc.), WebAssembly implementations will either want the
// unaligned access or they'll split anyway.
- if (Fast)
- *Fast = true;
+ if (Fast) *Fast = true;
return true;
}
@@ -271,9 +266,8 @@ static bool CallingConvSupported(Calling
CallConv == CallingConv::CXX_FAST_TLS;
}
-SDValue
-WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
- SmallVectorImpl<SDValue> &InVals) const {
+SDValue WebAssemblyTargetLowering::LowerCall(
+ CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;
SDLoc DL = CLI.DL;
SDValue Chain = CLI.Chain;
@@ -523,21 +517,21 @@ SDValue WebAssemblyTargetLowering::Lower
SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
- default:
- llvm_unreachable("unimplemented operation lowering");
- return SDValue();
- case ISD::FrameIndex:
- return LowerFrameIndex(Op, DAG);
- case ISD::GlobalAddress:
- return LowerGlobalAddress(Op, DAG);
- case ISD::ExternalSymbol:
- return LowerExternalSymbol(Op, DAG);
- case ISD::JumpTable:
- return LowerJumpTable(Op, DAG);
- case ISD::BR_JT:
- return LowerBR_JT(Op, DAG);
- case ISD::VASTART:
- return LowerVASTART(Op, DAG);
+ default:
+ llvm_unreachable("unimplemented operation lowering");
+ return SDValue();
+ case ISD::FrameIndex:
+ return LowerFrameIndex(Op, DAG);
+ case ISD::GlobalAddress:
+ return LowerGlobalAddress(Op, DAG);
+ case ISD::ExternalSymbol:
+ return LowerExternalSymbol(Op, DAG);
+ case ISD::JumpTable:
+ return LowerJumpTable(Op, DAG);
+ case ISD::BR_JT:
+ return LowerBR_JT(Op, DAG);
+ case ISD::VASTART:
+ return LowerVASTART(Op, DAG);
}
}
@@ -561,9 +555,8 @@ SDValue WebAssemblyTargetLowering::Lower
DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset()));
}
-SDValue
-WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue WebAssemblyTargetLowering::LowerExternalSymbol(
+ SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
const auto *ES = cast<ExternalSymbolSDNode>(Op);
EVT VT = Op.getValueType();
@@ -610,8 +603,7 @@ SDValue WebAssemblyTargetLowering::Lower
Ops.push_back(DAG.getBasicBlock(MBBs[0]));
// Add an operand for each case.
- for (auto MBB : MBBs)
- Ops.push_back(DAG.getBasicBlock(MBB));
+ for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB));
return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
}
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h?rev=260585&r1=260584&r2=260585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h Thu Feb 11 14:57:09 2016
@@ -29,17 +29,17 @@ enum NodeType : unsigned {
#undef HANDLE_NODETYPE
};
-} // end namespace WebAssemblyISD
+} // end namespace WebAssemblyISD
class WebAssemblySubtarget;
class WebAssemblyTargetMachine;
class WebAssemblyTargetLowering final : public TargetLowering {
-public:
+ public:
WebAssemblyTargetLowering(const TargetMachine &TM,
const WebAssemblySubtarget &STI);
-private:
+ private:
/// Keep a pointer to the WebAssemblySubtarget around so that we can make the
/// right decision when generating code for different targets.
const WebAssemblySubtarget *Subtarget;
@@ -49,9 +49,9 @@ private:
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
- std::pair<unsigned, const TargetRegisterClass *>
- getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
- StringRef Constraint, MVT VT) const override;
+ std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
+ const TargetRegisterInfo *TRI, StringRef Constraint,
+ MVT VT) const override;
bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override;
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
@@ -88,8 +88,8 @@ private:
namespace WebAssembly {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo);
-} // end namespace WebAssembly
+} // end namespace WebAssembly
-} // end namespace llvm
+} // end namespace llvm
#endif
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