[PATCH] D17041: [X86] Don't assume that a shuffle operand is #0: it isn't for VPERMV.

[Sanjay Patel via llvm-commits]

spatel added a comment.

In http://reviews.llvm.org/D17041#348716, @ab wrote:

> ..but now that I look it up, the AVX-512 intrinsics use the instruction order *sigh*
>  Back to square one.


Wow. Is it too late for Intel to fix/deprecate/rename those intrinsics? If the argument is that the intrinsics should match the asm, then what happened with the AVX2 vperm variants?


http://reviews.llvm.org/D17041