[llvm] r260131 - AArch64: match correct order in subtraction pattern.

[Hans Wennborg via llvm-commits]

Yes, go ahead.

Thanks,
Hans

On Mon, Feb 8, 2016 at 11:49 AM, Tim Northover <t.p.northover at gmail.com> wrote:
> Hi Hans,
>
> This one should probably go on release_38 too, if the branch is still
> open. At least here it affects 447.dealII from SPEC.
>
> OK for me to merge it?
>
> Tim.
>
> On 8 February 2016 at 11:33, Tim Northover via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>> AArch64: match correct order in subtraction pattern.
>>
>> The accumulator in multiply-and-subtract instructions is actually subtracted
>> *from* so these patterns were computing the wrong value.
>>
>> Modified:
>>     llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>>     llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=260131&r1=260130&r2=260131&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Feb  8 13:33:18 2016
>> @@ -766,12 +766,12 @@ def : Pat<(i64 (add (mul (sext_inreg GPR
>>            (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
>>                       (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
>>
>> -def : Pat<(i64 (sub (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),
>> +def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
>>            (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
>> -def : Pat<(i64 (sub (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),
>> +def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
>>            (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
>> -def : Pat<(i64 (sub (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)),
>> -                    GPR64:$Ra)),
>> +def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32),
>> +                                    (s64imm_32bit:$C)))),
>>            (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
>>                       (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
>>  } // AddedComplexity = 5
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll?rev=260131&r1=260130&r2=260131&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/arm64-mul.ll Mon Feb  8 13:33:18 2016
>> @@ -137,6 +137,16 @@ entry:
>>  ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
>>    %tmp1 = zext i32 %a to i64
>>    %tmp3 = mul i64 %tmp1, 12345678
>> -  %tmp4 = sub i64 %tmp3, %b
>> +  %tmp4 = sub i64 %b, %tmp3
>> +  ret i64 %tmp4
>> +}
>> +
>> +define i64 @t14(i32 %a, i64 %b) nounwind {
>> +entry:
>> +; CHECK-LABEL: t14:
>> +; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
>> +  %tmp1 = sext i32 %a to i64
>> +  %tmp3 = mul i64 %tmp1, -12345678
>> +  %tmp4 = sub i64 %b, %tmp3
>>    ret i64 %tmp4
>>  }
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits