[PATCH] D16956: [X86][SSE1] Add MOVLHPS/MOVHLPS lowering and memory folding support

[Simon Pilgrim via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: qcolombet, delena, andreadb, spatel.
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As discussed on PR26491, this patch adds support for lowering v4f32 shuffles to the MOVLHPS/MOVHLPS instructions. It also adds support for memory folding with their MOVLPS/MOVHPS load equivalents.

This first patch only really helps SSE1 targets as SSE2+ targets will widen the shuffle mask and use v2f64 equivalents (although they still combine to MOVLHPS/MOVHLPS for v2f64 splats). This will have to be addressed in a future patch, most likely when we add support for binary target shuffle combines.

Repository:
  rL LLVM

http://reviews.llvm.org/D16956

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/vector-shuffle-sse1.ll

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