[PATCH] D16918: [mips][microMIPS] Implement LLX, LLXE, SCX and SCXE instructions

[Daniel Sanders via llvm-commits]

dsanders requested changes to this revision.
dsanders added a comment.
This revision now requires changes to proceed.

Hi Zlatko,

I understand that llx/scx/llxe/scxe are about to be significantly changed in the documentation. I therefore think it's best to defer this patch for now and come back to it later.


================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:267-282
@@ -266,18 +266,18 @@
 class LLEBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+  InstSE<(outs RO:$rt), (ins mem_simm9gpr:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm9";
   let mayLoad = 1;
 }
 
 class SCBaseMM<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm12";
   let mayStore = 1;
   let Constraints = "$rt = $dst";
 }
 
 class SCEBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+  InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9gpr:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
----------------
This bit should still be fixed though. lle/sce have always has 9-bit offsets on microMIPS
Could you split it into a separate patch along with the relevant test cases?


http://reviews.llvm.org/D16918