[PATCH] D16291: AArch64: Implement missed conditional compare sequences.

Marcello Maggioni via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 3 17:12:00 PST 2016


I’m experiencing problems after this commit.

The changes the check for OR formation in the DAGCombiner from:

 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&


 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::OR, VT)) &&

For us 64-bit ORs are not legal, so we have custom lowering transforming them into ADDs
This combine turns them back to ORs creating a cycle in the Combiner that never terminates.

What’s the reasoning behind this change here? Making it LegalOrCustom could actually endup in a problem like this if the lowering for ORs happens to be turning into ADD and goes against the principle that usually Legal things are cheap and Custom things are not.


> On 1 Feb 2016, at 11:17, Balaram Makam via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> This revision was automatically updated to reflect the committed changes.
> Closed by commit rL259387: AArch64: Implement missed conditional compare sequences. (authored by bmakam).
> Changed prior to commit:
>  http://reviews.llvm.org/D16291?vs=46546&id=46561#toc
> Repository:
>  rL LLVM
> http://reviews.llvm.org/D16291
> Files:
>  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
>  llvm/trunk/test/CodeGen/AArch64/arm64-ccmp.ll
> <D16291.46561.patch>_______________________________________________
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