[PATCH] D16829: An implementation of Swing Modulo Scheduling
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Wed Feb 3 04:27:18 PST 2016
materi added a comment.
This looks like a nice SMS implementation!
I have also implemented SMS in LLVM (in a completely out-of-tree target). My target is also a VLIW where software pipelining is very important. We did the implementation after the register coalescer because that's where our normal VLIW scheduler operated. Your implementation is earlier which seems to be better in some ways (you can use phi-nodes in a nice way).
Have you considered implementing bundling before regalloc? It seems like this could be advantageous since some false live range interferences can be avoided.
Comment at: lib/CodeGen/MachinePipeliner.cpp:3057-3059
@@ +3056,5 @@
+// Create branches from each prolog basic block to the appropriate epilog
+// block. These edges are needed if the loop ends before reaching the
+void SwingSchedulerDAG::addBranches(MBBVectorTy &PrologBBs,
I do not understand how this works when more than one iteration starts to execute in the prolog.
For example if the runtime trip count is 1, and 2 iterations are started in the prolog. Don't you miss executing some instructions from the only loop iteration?
If this is not a bug, maybe you can add a test case that shows how this works?
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