[PATCH] D16768: [X86][AVX] Add support for 64-bit VZEXT_LOAD of 256-bit vectors to EltsFromConsecutiveLoads

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:5644
@@ +5643,3 @@
+      ((VT.is128BitVector() && TLI.isTypeLegal(MVT::v2i64)) ||
+       (VT.is256BitVector() && TLI.isTypeLegal(MVT::v4i64)))) {
+    EVT VecVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
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Could you, please, add 512 bit vector here?

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Comment at: lib/Target/X86/X86InstrSSE.td:5061
@@ -5060,1 +5060,3 @@
             (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
+  def : Pat<(v4i64 (X86vzload addr:$src)),
+            (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
----------------
The same pattern should be added to X86InstAVX512.td, right?


Repository:
  rL LLVM

http://reviews.llvm.org/D16768