[PATCH] D16723: [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target.

Sam Kolton via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 1 06:09:30 PST 2016

SamWot added a comment.

Last uploaded diff unfortunately contains new changes from LLVM master.  Comparing it with previous diff will show changes from master.

Comment at: lib/Target/AMDGPU/AMDGPU.td:306
@@ -305,2 +305,3 @@
   let guessInstructionProperties = 1;
+  let decodePositionallyEncodedOperands = 1;
   let noNamedPositionallyEncodedOperands = 1;
arsenm wrote:
> Do we need this? Ideally we would only use the names
This is needed now. Otherwise LLVM generate invalid decoder methods for most instructions. It tries to match operand names with names of fileds that specify operands in instruction encoding. E.g. for V_MOV_B32 operand names are "dst" and "src0" and fields names are "vdst" and "src0". So LLVM fail to match destination operand ("vdst" vs. "dst") and doesn't generate decoding method for it. Same time it match "src0" operand and tries to decode it successfully.
So until we fix names of operands using this option is only reasonable choice.

Comment at: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:113
@@ +112,3 @@
+DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const {
+  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
arsenm wrote:
> It looks like this doesn't handle using one of the literal constants for an 64-bit/f64 operand, which does work.
Disassembler for now support only 32-bit operands. Support for 64-bit operands is planned to be next step.


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