[PATCH] D14260: Optimize store of "bitcast" from vector to aggregate.

[Arch D. Robison via llvm-commits]

ArchDRobison updated this revision to Diff 46407.
ArchDRobison marked 2 inline comments as done.
ArchDRobison added a comment.

Two changes inspired by mzolokhin's comments for http://reviews.llvm.org/D14185:

- CHECK-LABEL added to tests.
- getTypeStoreSizeInBits used for size comparisons.

The choice between using getTypeSizeInBits or getTypeStoreSizeInBits  is not obvious to me, but the latter seems more appropriate because the issue is where type-punning a memory location is allowed, not whether address arithmetic is isomorphic.  For example, consider a hypothetical architecture requires 32-bit alignment for everything, and has a i24 type and a packed <3 x i24> type.  In this scenario, a struct {i24,i24,i24} will have 3 pad bytes interspersed, whereas a <3 x i24> will have the pad bytes at the end.  If someone has a more realistic example, I'd like to be enlightened.


http://reviews.llvm.org/D14260

Files:
  lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  test/Transforms/InstCombine/insert-val-extract-elem.ll

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