[PATCH] D8705: ScheduleDAGInstrs::buildSchedGraph() handling of memory dependecies rewritten.

Geoff Berry via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 29 12:13:11 PST 2016

gberry added inline comments.

Comment at: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll:11
@@ -10,2 +10,3 @@
 ; CHECK-NEXT:    val SU(5): Latency=4 Reg=%vreg2
-; CHECK-NEXT:    ch  SU(4): Latency=0
+; CHECK-NEXT:    ch  SU(3): Latency=0
+; CHECK: SU(3):   STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
I'm not sure I follow the reasoning behind this change.  It seems like this is a regression.  The 3->4 edge (load %ptr1_plus1 -> store %ptr1) should be unnecessary since areMemAccessTriviallyDisjoint can tell you these two accesses don't overlap.


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