[PATCH] D16729: [X86][SSE] Add general 32-bit LOAD + VZEXT_MOVL support to EltsFromConsecutiveLoads

[Simon Pilgrim via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: qcolombet, spatel, mkuper.
RKSimon added a subscriber: llvm-commits.
RKSimon set the repository for this revision to rL LLVM.

This patch adds support for consecutive (load/undef elements) 32-bit loads, followed by trailing undef/zero elements to be combined to a single MOVSS load.

Follow up to D16217

Note: I've been looking into correcting the domain for both the MOVSS/MOVD and the MOVSD/MOVQ load/stores but am concerned about the number of test changes - is this something that people think is worthwhile? I'd probably have to change many of the tests to ensure that they keep to the intended domain,

Repository:
  rL LLVM

http://reviews.llvm.org/D16729

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/merge-consecutive-loads-128.ll
  test/CodeGen/X86/merge-consecutive-loads-256.ll

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