[PATCH] D16110: [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic

Kit Barton via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 27 13:14:15 PST 2016

kbarton added inline comments.

Comment at: lib/Target/PowerPC/PPC.td:129
@@ -127,1 +128,3 @@
+                                        "Enable POWER9 instructions",
+                                        [FeatureP8Crypto, FeatureP8Vector]>;
 def FeatureDirectMove :
Why are we creating a P9 feature?
For other processors we have defined a processor model, which is a composition of other features (see P7Model and P8Model). 
We need to think very carefully about how we want these models to be composed, and what can be enabled/disabled as a result of that composition (and whether that is useful). I'm not immediately convinced this is the best way to handle it.  

Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1776
@@ +1775,3 @@
+  // X_VT5_XO5_VB5 represents [PO VRT XO VRB XO /], usually means VRT = op VRB.
+  // TODO: Add intrinsic support, like "class VX1_Int_Ty" in PPCInstrAltivec.td
+  class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
I would prefer to track this in a separate file. 

Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1792
@@ +1791,3 @@
+  // means VRT = VRA op VRB.
+  // TODO: Add intrinsic support, or map to llvm instruction
+  class X1_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
Same comment about tracking TODOs


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