[PATCH] D15927: ScheduleDAGInstrs: Bug fix for missed memory dependency.

[Geoff Berry via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL256950: ScheduleDAGInstrs: Bug fix for missed memory dependency. (authored by gberry).

Changed prior to commit:
  http://reviews.llvm.org/D15927?vs=44125&id=44128#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D15927

Files:
  llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll

Index: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -1005,6 +1005,9 @@
           addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
                              I->second[i], RejectMemNodes, TrueMemOrderLatency);
       }
+      // This call must come after calls to addChainDependency() since it
+      // consumes the 'RejectMemNodes' list that addChainDependency() possibly
+      // adds to.
       adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
                       TrueMemOrderLatency);
       PendingLoads.clear();
@@ -1086,6 +1089,9 @@
           addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
                              RejectMemNodes);
       }
+      // This call must come after calls to addChainDependency() since it
+      // consumes the 'RejectMemNodes' list that addChainDependency() possibly
+      // adds to.
       adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
                       TrueMemOrderLatency);
     } else if (MI->mayLoad()) {
@@ -1133,13 +1139,16 @@
           else
             NonAliasMemUses[V].push_back(SU);
         }
-        if (MayAlias)
-          adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU,
-                          RejectMemNodes, /*Latency=*/0);
         // Add dependencies on alias and barrier chains, if needed.
         if (MayAlias && AliasChain)
           addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
                              RejectMemNodes);
+        if (MayAlias)
+          // This call must come after calls to addChainDependency() since it
+          // consumes the 'RejectMemNodes' list that addChainDependency()
+          // possibly adds to.
+          adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU,
+                          RejectMemNodes, /*Latency=*/0);
         if (BarrierChain)
           BarrierChain->addPred(SDep(SU, SDep::Barrier));
       }
Index: llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -0,0 +1,22 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+;
+; Test for bug in misched memory dependency calculation.
+;
+; CHECK: ********** MI Scheduling **********
+; CHECK: misched_bug:BB#0 entry
+; CHECK: SU(2):   %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
+; CHECK:   Successors:
+; CHECK-NEXT:    val SU(5): Latency=4 Reg=%vreg2
+; CHECK-NEXT:    ch  SU(4): Latency=0
+; CHECK: SU(4):   STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
+; CHECK: SU(5):   %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: ** ScheduleDAGMI::schedule picking next node
+define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
+entry:
+  %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
+  %val1 = load i32, i32* %ptr1_plus1, align 4
+  store i32 0, i32* %ptr1, align 4
+  store i32 0, i32* %ptr2, align 4
+  ret i32 %val1
+}


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