[PATCH] D15872: AMDGPU: Remove redundant let mayLoad = 1

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 4 14:13:38 PST 2016


arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm.

This is already set on the SMRD format class.

http://reviews.llvm.org/D15872

Files:
  lib/Target/AMDGPU/SIInstructions.td

Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -59,8 +59,6 @@
 // SMRD Instructions
 //===----------------------------------------------------------------------===//
 
-let mayLoad = 1 in {
-
 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
 // SMRD instructions, because the SGPR_32 register class does not include M0
 // and writing to M0 from an SMRD instruction will hang the GPU.
@@ -90,8 +88,6 @@
   smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
 >;
 
-} // mayLoad = 1
-
 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;
 
 defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D15872.43923.patch
Type: text/x-patch
Size: 787 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160104/4f9027a9/attachment.bin>


More information about the llvm-commits mailing list