[PATCH] D15703: [AVR] Add instruction definitions

Dylan McKay via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 23 01:18:55 PST 2015

dylanmckay marked 3 inline comments as done.

Comment at: lib/Target/AVR/AVRInstrInfo.td:58
@@ +57,3 @@
+// shift nodes
+def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
+def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
rjordans wrote:
> arsenm wrote:
> > These custom shift nodes look strange. It looks like the shift amount is passed in an implicit register, but you aren't adding glue to the node for the copy into it
> AVR only has shift-by-1 kind of operations so they don't get a shift amount specified through a register
@rjordans is right, which also makes for repetitive code generated for shifts bigger than one bit.

Comment at: lib/Target/AVR/AVRInstrInfo.td:1961
@@ +1960,3 @@
+// :FIXME: DAGCombiner produces an shl node after legalization from these seq:
+// BR_JT -> (mul x, 2) -> (shl x, 1)
arsenm wrote:
> Can you add an xfailed test for this
Not yet, as the lowering code has not been merged currently. I will add it to a TODO list in `lib/Target/AVR` however.


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