[PATCH] D15713: AVX512BW: Enable packed word shift for 512bit vector.

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:18299
@@ -18297,1 +18298,3 @@
+  if (VT.getScalarSizeInBits() == 16)
+    return (Subtarget->hasBWI() && (VT.is512BitVector() || Subtarget->hasVLX()));
 
----------------
you can add a pattern to .td file for extending 256 and 128 to 512 and you'll not need the VLX checks

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:18366
@@ -18362,1 +18365,3 @@
+          (Subtarget->hasInt256() && VT == MVT::v32i8) ||
+          (Subtarget->hasBWI() && VT == MVT::v64i8)) {
         unsigned NumElts = VT.getVectorNumElements();
----------------
64i8 is legal on bwi only.


Repository:
  rL LLVM

http://reviews.llvm.org/D15713