[llvm] r256152 - [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 21 05:08:59 PST 2015
Author: zbuljan
Date: Mon Dec 21 07:08:58 2015
New Revision: 256152
URL: http://llvm.org/viewvc/llvm-project?rev=256152&view=rev
Log:
[mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions
Differential Revision: http://reviews.llvm.org/D15570
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
llvm/trunk/test/MC/Mips/mips32r2/invalid.s
llvm/trunk/test/MC/Mips/mips64r2/invalid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Dec 21 07:08:58 2015
@@ -3636,9 +3636,15 @@ bool MipsAsmParser::MatchAndEmitInstruct
case Match_UImm5_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 5-bit unsigned immediate");
+ case Match_UImm5_1:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range 1 .. 32");
case Match_UImm5_32:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range 32 .. 63");
+ case Match_UImm5_33:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range 33 .. 64");
case Match_UImm5_0_Report_UImm6:
// This is used on UImm5 operands that have a corresponding UImm5_32
// operand to avoid confusing the user.
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon Dec 21 07:08:58 2015
@@ -396,11 +396,6 @@ static DecodeStatus DecodeInsSize(MCInst
uint64_t Address,
const void *Decoder);
-static DecodeStatus DecodeExtSize(MCInst &Inst,
- unsigned Insn,
- uint64_t Address,
- const void *Decoder);
-
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
@@ -1964,15 +1959,6 @@ static DecodeStatus DecodeInsSize(MCInst
Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
-
-static DecodeStatus DecodeExtSize(MCInst &Inst,
- unsigned Insn,
- uint64_t Address,
- const void *Decoder) {
- int Size = (int) Insn + 1;
- Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
- return MCDisassembler::Success;
-}
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Mon Dec 21 07:08:58 2015
@@ -865,15 +865,6 @@ getMemEncodingMMImm4sp(const MCInst &MI,
return ((OffBits >> 2) & 0x0F);
}
-unsigned
-MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
- assert(MI.getOperand(OpNo).isImm());
- unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
- return SizeEncoding - 1;
-}
-
// FIXME: should be called getMSBEncoding
//
unsigned
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h Mon Dec 21 07:08:58 2015
@@ -191,9 +191,6 @@ public:
unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const;
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Mon Dec 21 07:08:58 2015
@@ -473,12 +473,13 @@ class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<b
let Inst{15-0} = offset;
}
-class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
+class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
+ : MMR6Arch<instr_asm> {
bits<32> Inst;
let Inst{31-26} = 0x00;
let Inst{25-16} = 0x00;
- let Inst{15-6} = 0x3cd;
+ let Inst{15-6} = funct;
let Inst{5-0} = 0x3c;
}
@@ -513,7 +514,8 @@ class BARRIER_MMR6_ENC<string instr_asm,
let Inst{5-0} = 0x0;
}
-class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
+class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
+ : MMR6Arch<instr_asm> {
bits<32> Inst;
bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon Dec 21 07:08:58 2015
@@ -52,8 +52,10 @@ class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<
class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
-class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
-class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
+class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
+class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
+class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
+class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
@@ -361,8 +363,10 @@ class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_
class EHB_MMR6_DESC : Barrier<"ehb">;
class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
+class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>;
class ERET_MMR6_DESC : ER_FT<"eret">;
+class DERET_MMR6_DESC : ER_FT<"deret">;
class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
@@ -968,7 +972,9 @@ def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC,
def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
-def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
+def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
+def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
+def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
ISA_MICROMIPS32R6;
def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
@@ -1205,6 +1211,7 @@ def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_M
//===----------------------------------------------------------------------===//
def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
+def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
!strconcat("b", "\t$offset")> {
Modified: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td Mon Dec 21 07:08:58 2015
@@ -55,21 +55,25 @@ class DAHI_MMR6_DESC : DAHI_DATI_DESC_BA
class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
- SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>, MipsR6Inst {
+ Operand SizeOpnd, SDPatternOperator Op = null_frag>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
dag OutOperandList = (outs RO:$rt);
- dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size);
+ dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
InstrItinClass Itinerary = II_EXT;
Format Form = FrmR;
string BaseOpcode = instr_asm;
}
-class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6,
- MipsExt>;
+// TODO: Add 'pos + size' constraint check to dext* instructions
+// DEXT: 0 < pos + size <= 63
+// DEXTM, DEXTU: 32 < pos + size <= 64
+class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5,
+ uimm5_plus1, MipsExt>;
class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
- MipsExt>;
+ uimm5_plus33, MipsExt>;
class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
- MipsExt>;
+ uimm5_plus1, MipsExt>;
class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Mon Dec 21 07:08:58 2015
@@ -844,9 +844,9 @@ let DecoderNamespace = "MicroMips", Pred
/// Word Swap Bytes Within Halfwords
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
-
- def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
- EXT_FM_MM<0x2c>;
+ // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
+ def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,
+ MipsExt>, EXT_FM_MM<0x2c>;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
EXT_FM_MM<0x0c>;
@@ -1018,6 +1018,7 @@ def B_MM_Pseudo : UncondBranchMMPseudo<"
let Predicates = [InMicroMips] in {
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
+def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tge $rs, $rt",
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Dec 21 07:08:58 2015
@@ -273,9 +273,15 @@ let isCodeGenOnly = 1 in
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
let AdditionalPredicates = [NotInMicroMips] in {
- def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
- def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
- def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32>, EXT_FM<2>;
+ // TODO: Add 'pos + size' constraint check to dext* instructions
+ // DEXT: 0 < pos + size <= 63
+ // DEXTM, DEXTU: 32 < pos + size <= 64
+ def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>,
+ EXT_FM<3>;
+ def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>,
+ EXT_FM<1>;
+ def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
+ MipsExt>, EXT_FM<2>;
}
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Dec 21 07:08:58 2015
@@ -413,8 +413,12 @@ def ConstantUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
def ConstantSImm6AsmOperandClass
: ConstantSImmAsmOperandClass<6, [ConstantUImm7AsmOperandClass]>;
+def ConstantUImm5Plus1AsmOperandClass
+ : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 1>;
def ConstantUImm5Plus32AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>;
+def ConstantUImm5Plus33AsmOperandClass
+ : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 33>;
def ConstantUImm5Plus32NormalizeAsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> {
let Name = "ConstantUImm5_32_Norm";
@@ -536,11 +540,25 @@ def uimm2_plus1 : Operand<i32> {
let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
}
+def uimm5_plus1 : Operand<i32> {
+ let PrintMethod = "printUnsignedImm";
+ let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
+ let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
+ let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;
+}
+
def uimm5_plus32 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
}
+def uimm5_plus33 : Operand<i32> {
+ let PrintMethod = "printUnsignedImm";
+ let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
+ let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
+ let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass;
+}
+
def uimm5_plus32_normalize : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
@@ -683,12 +701,6 @@ def PtrRC : Operand<iPTR> {
let ParserMatchClass = GPR32AsmOperand;
}
-// size operand of ext instruction
-def size_ext : Operand<i32> {
- let EncoderMethod = "getSizeExtEncoding";
- let DecoderMethod = "DecodeExtSize";
-}
-
// size operand of ins instruction
def size_ins : Operand<i32> {
let EncoderMethod = "getSizeInsEncoding";
@@ -1187,8 +1199,8 @@ class ReadHardware<RegisterOperand CPURe
// Ext and Ins
class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
- SDPatternOperator Op = null_frag>:
- InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
+ Operand SizeOpnd, SDPatternOperator Op = null_frag> :
+ InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
FrmR, opstr>, ISA_MIPS32R2;
@@ -1473,15 +1485,15 @@ def TRAP : TrapBase<BREAK>;
def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
-def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
-def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
+ def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
+ def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
+ def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
}
-def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
let AdditionalPredicates = [NotInMicroMips] in {
-def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
+ def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
+ def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
}
-def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
AdditionalPredicates = [NotInMicroMips] in {
@@ -1676,7 +1688,9 @@ def PseudoUDIV : MultDivPseudo<UDIV, ACC
let AdditionalPredicates = [NotInMicroMips] in {
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
}
-def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
+// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
+def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>,
+ EXT_FM<0>;
def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
/// Move Control Registers From/To CPU Registers
@@ -1871,9 +1885,9 @@ def : MipsInstAlias<"syscall", (SYSCALL
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
let AdditionalPredicates = [NotInMicroMips] in {
-def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
+ def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
+ def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
}
-def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Mon Dec 21 07:08:58 2015
@@ -53,6 +53,7 @@
0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5)
0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x00 0x00 0xe3 0x7c # CHECK: deret
0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
0x00 0x00 0x18 0x00 # CHECK: ehb
@@ -253,3 +254,5 @@
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
+0x00 0x00 0x47 0x7c # CHECK: di
+0x00 0x0f 0x47 0x7c # CHECK: di $15
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt Mon Dec 21 07:08:58 2015
@@ -166,3 +166,6 @@
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
+0x00 0x00 0xe3 0x7c # CHECK: deret
+0x00 0x00 0x47 0x7c # CHECK: di
+0x00 0x0f 0x47 0x7c # CHECK: di $15
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Mon Dec 21 07:08:58 2015
@@ -11,8 +11,11 @@
break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
+ # FIXME: Check '0 < pos + size <= 32' constraint on ext
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
+ ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jraddiusp -1 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Mon Dec 21 07:08:58 2015
@@ -25,8 +25,11 @@
break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
+ # FIXME: Check '0 < pos + size <= 32' constraint on ext
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
+ ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Mon Dec 21 07:08:58 2015
@@ -45,6 +45,9 @@
ei # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $0 # CHECK: ei # encoding: [0x00,0x00,0x57,0x7c]
ei $10 # CHECK: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
+ di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
+ di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
+ di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c]
eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c]
jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b]
@@ -246,3 +249,4 @@
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
+ deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Mon Dec 21 07:08:58 2015
@@ -18,13 +18,21 @@
bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
- # FIXME: Check size on dext*
- dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
- dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
+ # FIXME: Check various 'pos + size' constraints on dext*
+ dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
+ dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
+ dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
+ dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
+ dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
+ dextm $2, $3, 1, 32 # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64
+ dextm $2, $3, 1, 65 # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64
dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
+ dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
+ dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
# FIXME: Check size on dins*
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
@@ -32,8 +40,11 @@
dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
+ # FIXME: Check '0 < pos + size <= 32' constraint on ext
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
+ ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Mon Dec 21 07:08:58 2015
@@ -18,7 +18,7 @@ a:
dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04]
dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04]
dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec]
- dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4]
+ dextm $9, $6, 3, 39 # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4]
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
@@ -146,5 +146,9 @@ a:
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
+ deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
+ di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
+ di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
+ di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
1:
Modified: llvm/trunk/test/MC/Mips/mips32r2/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/invalid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/invalid.s Mon Dec 21 07:08:58 2015
@@ -8,9 +8,11 @@
.set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
- # FIXME: Check size on ext
+ # FIXME: Check '0 < pos + size <= 32' constraint on ext
ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+ ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32
+ ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32
# FIXME: Check size on ins
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/mips64r2/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/invalid.s?rev=256152&r1=256151&r2=256152&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/invalid.s Mon Dec 21 07:08:58 2015
@@ -8,13 +8,21 @@
.set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
- # FIXME: Check size on dext*
- dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
- dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
+ # FIXME: Check various 'pos + size' constraints on dext*
+ dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
+ dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
+ dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
+ dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
+ dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
+ dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
+ dextm $2, $3, 1, 32 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64
+ dextm $2, $3, 1, 65 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64
dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
+ dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
+ dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
# FIXME: Check size on dins*
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
@@ -38,9 +46,11 @@
dsra $2, $3, 64 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsra32 $2, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsra32 $2, $3, 64 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
- # FIXME: Check size on ext
+ # FIXME: Check '0 < pos + size <= 32' constraint on ext
ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+ ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32
+ ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:24: error: expected immediate in range 1 .. 32
# FIXME: Check size on ins
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
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