[PATCH] D15515: [AArch64] Add DAG combine for extract extend pattern

[Matthew Simpson via llvm-commits]

mssimpso added a comment.

Thanks very much Silviu, James, Geoff, and Chad for the feedback.

I reverted this patch because it was breaking some internal tests. After looking at the failing test case, I don't think the DAG is the right place to do this. The issue in the failing test was that the sign_extend was first matched to another pattern (a widening operation like ssubw).  Without the sign_extend, the widened extract_vector_elt could no longer be matched to anything. See the code below for an example.

  define i64 @f(<8 x i16> %a, i64 %b) {
    %d = extractelement <8 x i16> %a, i32 2
    %e = sext i16 %d to i64
    %t1 = sub nsw i64 %b, %e
    ret i64 %t1
  }

I think the initial revision of the patch, which added the two additional patterns to the target description, is the safer approach. We'll match the smov cases, but won't risk making the DAG illegal. Were there any objections to the initial revision?


Repository:
  rL LLVM

http://reviews.llvm.org/D15515