[PATCH] D15417: [mips][microMIPS] Implement BEQZC and BNEZC instructions

[Daniel Sanders via llvm-commits]

dsanders requested changes to this revision.
This revision now requires changes to proceed.

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Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:1842-1844
@@ +1841,5 @@
+static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst,
+  unsigned Offset,
+  uint64_t Address,
+  const void *Decoder) {
+  int32_t BranchOffset = SignExtend32<21>(Offset) << 1;
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Indentation

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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:333-336
@@ +332,6 @@
+/// relocation, record the relocation and return zero.
+unsigned MipsMCCodeEmitter::
+getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
+SmallVectorImpl<MCFixup> &Fixups,
+const MCSubtargetInfo &STI) const {
+
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Formatting

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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:346
@@ +345,3 @@
+
+  // TODO: Push fixup.
+  return 0;
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Shouldn't this be filled in? The previous patch (D15526) added the necessary fixup.

Could you also add a test case covering this path?

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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h:137-138
@@ +136,4 @@
+  unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
+    SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const;
+
----------------
Indentation


http://reviews.llvm.org/D15417