[llvm] r255796 - AMDGPU: Override getCFInstrCost

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Dec 16 12:37:19 2015
New Revision: 255796

URL: http://llvm.org/viewvc/llvm-project?rev=255796&view=rev
Log:
AMDGPU: Override getCFInstrCost

The default cost was 0 with the assumption that it is predictable.

Added:
    llvm/trunk/test/Analysis/CostModel/AMDGPU/br.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp?rev=255796&r1=255795&r2=255796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp Wed Dec 16 12:37:19 2015
@@ -81,6 +81,17 @@ unsigned AMDGPUTTIImpl::getMaxInterleave
   return 64;
 }
 
+unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
+  // XXX - For some reason this isn't called for switch.
+  switch (Opcode) {
+  case Instruction::Br:
+  case Instruction::Ret:
+    return 10;
+  default:
+    return BaseT::getCFInstrCost(Opcode);
+  }
+}
+
 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
                                       unsigned Index) {
   switch (Opcode) {

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h?rev=255796&r1=255795&r2=255796&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h Wed Dec 16 12:37:19 2015
@@ -61,6 +61,8 @@ public:
   unsigned getRegisterBitWidth(bool Vector);
   unsigned getMaxInterleaveFactor(unsigned VF);
 
+  unsigned getCFInstrCost(unsigned Opcode);
+
   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
   bool isSourceOfDivergence(const Value *V) const;
 };

Added: llvm/trunk/test/Analysis/CostModel/AMDGPU/br.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/AMDGPU/br.ll?rev=255796&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/AMDGPU/br.ll (added)
+++ llvm/trunk/test/Analysis/CostModel/AMDGPU/br.ll Wed Dec 16 12:37:19 2015
@@ -0,0 +1,45 @@
+; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
+
+; CHECK: 'test_br_cost'
+; CHECK: estimated cost of 10 for instruction: br i1
+; CHECK: estimated cost of 10 for instruction: br label
+; CHECK: estimated cost of 10 for instruction: ret void
+define void @test_br_cost(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 {
+bb0:
+  br i1 undef, label %bb1, label %bb2
+
+bb1:
+  %vec = load i32, i32 addrspace(1)* %vaddr
+  %add = add i32 %vec, %b
+  store i32 %add, i32 addrspace(1)* %out
+  br label %bb2
+
+bb2:
+  ret void
+
+}
+
+; CHECK: 'test_switch_cost'
+; CHECK: Unknown cost for instruction:   switch
+define void @test_switch_cost(i32 %a) #0 {
+entry:
+  switch i32 %a, label %default [
+    i32 0, label %case0
+    i32 1, label %case1
+  ]
+
+case0:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+case1:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+default:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+end:
+  ret void
+}