[llvm] r255501 - [Hexagon] Subtarget features/default CPU corrections
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 14 07:03:54 PST 2015
Author: kparzysz
Date: Mon Dec 14 09:03:54 2015
New Revision: 255501
URL: http://llvm.org/viewvc/llvm-project?rev=255501&view=rev
Log:
[Hexagon] Subtarget features/default CPU corrections
Modified:
llvm/trunk/lib/Target/Hexagon/Hexagon.td
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Mon Dec 14 09:03:54 2015
@@ -30,7 +30,7 @@ def ArchV60: SubtargetFeature<"v60", "He
// Hexagon ISA Extensions
def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
"true", "Hexagon HVX instructions">;
-def ExtensionHVXDbl: SubtargetFeature<"hvxDbl", "UseHVXDblOps",
+def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
"true", "Hexagon HVX Double instructions">;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Mon Dec 14 09:03:54 2015
@@ -61,9 +61,7 @@ void HexagonSubtarget::initializeEnviron
HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
- // Default architecture.
- if (CPUString.empty())
- CPUString = "hexagonv60";
+ CPUString = HEXAGON_MC::selectHexagonCPU(getTargetTriple(), CPU);
static std::map<StringRef, HexagonArchEnum> CpuTable {
{ "hexagonv4", V4 },
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Mon Dec 14 09:03:54 2015
@@ -112,7 +112,7 @@ public:
return Hexagon_SMALL_DATA_THRESHOLD;
}
const HexagonArchEnum &getHexagonArchVersion() const {
- return HexagonArchVersion;
+ return HexagonArchVersion;
}
};
Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Mon Dec 14 09:03:54 2015
@@ -126,8 +126,9 @@ HexagonTargetMachine::HexagonTargetMachi
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
- : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
- Options, RM, CM, OL),
+ : LLVMTargetMachine(T, "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-"
+ "i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-"
+ "n16:32", TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()) {
initAsmInfo();
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Mon Dec 14 09:03:54 2015
@@ -48,6 +48,12 @@ cl::opt<bool> llvm::HexagonDisableDuplex
("mno-pairing",
cl::desc("Disable looking for duplex instructions for Hexagon"));
+StringRef HEXAGON_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) {
+ if (CPU.empty())
+ CPU = "hexagonv60";
+ return CPU;
+}
+
MCInstrInfo *llvm::createHexagonMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitHexagonMCInstrInfo(X);
@@ -62,10 +68,8 @@ static MCRegisterInfo *createHexagonMCRe
static MCSubtargetInfo *
createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
- StringRef CPUName = CPU;
- if (CPU.empty())
- CPUName = "hexagonv5";
- return createHexagonMCSubtargetInfoImpl(TT, CPUName, FS);
+ CPU = HEXAGON_MC::selectHexagonCPU(TT, CPU);
+ return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
}
namespace {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=255501&r1=255500&r2=255501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Mon Dec 14 09:03:54 2015
@@ -41,17 +41,21 @@ extern const InstrStage HexagonStages[];
MCInstrInfo *createHexagonMCInstrInfo();
-MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
- MCRegisterInfo const &MRI,
+MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCRegisterInfo &MRI,
MCContext &MCT);
-MCAsmBackend *createHexagonAsmBackend(Target const &T,
- MCRegisterInfo const &MRI,
+MCAsmBackend *createHexagonAsmBackend(const Target &T,
+ const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, StringRef CPU);
+namespace HEXAGON_MC {
+ StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
+}
+
} // End llvm namespace
// Define symbolic names for Hexagon registers. This defines a mapping from
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