[llvm] r255112 - [mips][ias] Range check uimm10 operands
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 9 05:48:05 PST 2015
Author: dsanders
Date: Wed Dec 9 07:48:05 2015
New Revision: 255112
URL: http://llvm.org/viewvc/llvm-project?rev=255112&view=rev
Log:
[mips][ias] Range check uimm10 operands
Summary:
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15229
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips-invalid.s
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/mips32r6/invalid.s
llvm/trunk/test/MC/Mips/mips64r6/invalid.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Dec 9 07:48:05 2015
@@ -3653,6 +3653,9 @@ bool MipsAsmParser::MatchAndEmitInstruct
case Match_UImm8_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 8-bit unsigned immediate");
+ case Match_UImm10_0:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected 10-bit unsigned immediate");
}
llvm_unreachable("Implement any new match types added!");
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Dec 9 07:48:05 2015
@@ -394,8 +394,10 @@ class ConstantUImmAsmOperandClass<int Bi
let DiagnosticType = "UImm" # Bits # "_" # Offset;
}
+def ConstantUImm10AsmOperandClass
+ : ConstantUImmAsmOperandClass<10, []>;
def ConstantUImm8AsmOperandClass
- : ConstantUImmAsmOperandClass<8, []>;
+ : ConstantUImmAsmOperandClass<8, [ConstantUImm10AsmOperandClass]>;
def ConstantUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<6, [ConstantUImm8AsmOperandClass]>;
def ConstantUImm5Plus32AsmOperandClass
@@ -492,17 +494,6 @@ def simm32 : Operand<i32>;
def uimm20 : Operand<i32> {
}
-def MipsUImm10AsmOperand : AsmOperandClass {
- let Name = "UImm10";
- let RenderMethod = "addImmOperands";
- let ParserMethod = "parseImm";
- let PredicateMethod = "isUImm<10>";
-}
-
-def uimm10 : Operand<i32> {
- let ParserMatchClass = MipsUImm10AsmOperand;
-}
-
def simm16_64 : Operand<i64> {
let DecoderMethod = "DecodeSimm16";
}
@@ -514,7 +505,7 @@ def uimmz : Operand<i32> {
}
// Unsigned Operands
-foreach I = {1, 2, 3, 4, 5, 6, 8} in
+foreach I = {1, 2, 3, 4, 5, 6, 8, 10} in
def uimm # I : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let ParserMatchClass =
Modified: llvm/trunk/test/MC/Mips/micromips-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-invalid.s?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-invalid.s Wed Dec 9 07:48:05 2015
@@ -75,11 +75,6 @@
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Wed Dec 9 07:48:05 2015
@@ -1,6 +1,12 @@
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1
+ break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+ break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Wed Dec 9 07:48:05 2015
@@ -16,8 +16,12 @@
bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
- break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1023, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+ break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
@@ -68,6 +72,8 @@
tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate
+ wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate
wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Mips/mips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid.s?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid.s Wed Dec 9 07:48:05 2015
@@ -15,10 +15,12 @@ local_label:
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+ break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Modified: llvm/trunk/test/MC/Mips/mips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid.s?rev=255112&r1=255111&r2=255112&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s Wed Dec 9 07:48:05 2015
@@ -13,10 +13,12 @@ local_label:
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
+ break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+ break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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