[PATCH] D15256: ARM: Better codegen for 64-bit compares.

[Peter Collingbourne via llvm-commits]

pcc added inline comments.

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4720
@@ +4719,3 @@
+  SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
+                                   Cmp.getValue(1), SDValue());
+  return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
----------------
hans wrote:
> I'm too unfamiliar with ARM to follow this.
> 
> Should I understand it that Cmp.getValue(1) is something suitable to be moved into the flags register, and that makes it possible to do the CMOV below? (Which the BRCOND combine below will eliminate if we really want to branch on this rather than get a value?)
Yes, exactly. `Cmp.getValue(1)` represents the flags register itself; `ARMISD::CMOV` does not take a flags register as input so we need a `CopyToReg` to get the scheduling correct.


http://reviews.llvm.org/D15256